SRAM generating an echo clock signal

Details SRAM generating an echo clock signal SRAM generating an echo clock signal

2000-08-04

2001-08-21

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S189110

Reexamination Certificate

active

06278637

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a SRAM generating an echo clock signal and, more particularly, to a SRAM including an echo clock generator for generating an echo clock signal at the timing of the output of read data.
(b) Description of the Related Art
Recent developments of the performance of personal computers are partly due to a pipe-line processing and burst read SRAM (PBSRAM) which is used as a secondary cache memory in the personal computers. With the developments of the high-speed capability of the personal computers, the PBSRAM is also requested to have a higher-speed operational capability.
In a double data rate PBSRAM wherein two cell data are read out at a single clock cycle, the data are output at the rate corresponding to the frequency which is double the operational frequency of the PBSRAM. For example, for an operational frequency of 250 MHz or a clock cycle of 4 ns (nanosecond) of the DDR-PBSRAM, the clock access rate corresponds to 2 ns or 500 MHz.
A new type of PBSRAM generates a reference signal called “echo clock signal”, which informs the timing of the output of read data to the CPU when the read data is delivered from the PBSRAM, thereby compensating the irregularity of the output timing of the read data.
FIG. 1A
shows a timing chart for the echo clock signal together with the read data in a single data rate PBSRAM (SDR-PBSRAM). In the drawing, CLK, ADD, AC and GW are external clock signal, address signal, address control signal and write enable signal, respectively, which are supplied from outside the PBSRAM. If the write enable signal GW assumes a high level when the address control signal AC is at a low level, the PBSRAM operates for reading data from memory cells, whereas if the write enable signal GW assumes a low level when the address control signal AC is at a low level, the PBSRAM operates for writing data to the memory cells.
The PBSRAM delivers a read data DQ and an echo clock signal KQ to the CPU in a read cycle. More specifically, the PBSRAM first fetches an address A
1
at a rising edge “a” of the clock signal CLK, delivers read data DQ
11
from the memory cell having the address A
1
together with an echo clock KQ signal at a next rising edge “b”. The PBSRAM also delivers read data DQ
12
to DQ
14
from the addresses succeeding the address A
1
together with respective echo clock signals Kq at the succeeding rising dges “c” to “e”, thereby executing a burst read operation. similarly, the PBSRAM fetches a next address A
2
at a next rising edge “f” and delivers read data DQ
21
, DQ
22
, . . . from the addresses starting from the address A
2
together with the echo clock signals KQ at the succeeding rising edges of the clock signal CLK.
In the SDR-PBSRAM, the rising edge of the echo clock signal KQ is used for a reference timing for compensating the irregularity of the output timing of the read data DQ. Thus, it is preferable that the timing difference TCHQV or TCHQX between the rising edge of the echo clock signal KQ and the start or end of the level shift caused by the corresponding read data DQ be as small as possible, in view of suppressing the irregularity of the timing difference between the read data and the echo clock signal.
FIG. 1B
shows a timing chart for the echo clock signal together with the read data in a double data rate PBSRAM (DDR-PBSRAM). In the DDR-PBSRAM, the timing of output of the read data resides at a rising edge of the echo clock signal KQ as well as a falling edge of the echo clock signal KQ. More specifically, for the read data DQn delivered at the timing of a rising edge of the echo clock signal KQ, the rising edge is the reference to the output timing of the read data, whereas for the read data DQm delivered at the timing of a falling edge of the echo clock signal KQ, the falling edge is the reference to the output timing of the read data. Thus, it is preferable that the timing difference TCHQV or TCLQV between a rising edge of the echo clock signal KQ and the start of the level shift caused by the read data DQ as well as the timing difference TCLQX or TCHQX between a falling edge of the echo clock signal KQ and the start of the level shift caused by the read data DQ be as small as possible.
With the development of higher-operational speed and larger number of bits in data processing by the personal computers, it is a principal subject of the DDR-PBSRAM to obtain an optimum timing between the output of the read data DQ and the echo clock signal KQ, in view that DDR-PBSRAM has a double read rate.
FIG. 2
shows a layout of a conventional DDR-PBSRAM. The DDR-PBSRAM includes a memory cell array
11
including a plurality of memory cells arrayed in a matrix, and a peripheral circuit for controlling the read/write operation for the memory cell array
11
. The external clock signal CLK fed through the external pad
10
is used for generating an internal clock signal CLKT which is in phase with the external clock signal CLK and controls the data output sections
2
a
to
2
h
and echo clock generators
3
a
to
3
d.
In the exemplified PBSRAM, each of the data output sections
2
a
to
2
h
includes four output members. The large number of the output members and the echo clock generators
3
a
to
3
d
disposed in a chip causes a distortion in the internal clock signal CLKT. The distortion in the internal clock signal CLKT generates a timing difference between a group of read data DQ
13
o DQ
16
and DQ
17
to DQ
20
output from the output sections
2
e
and
2
a
near the pad
10
and a group of read data DQ
1
to DQ
4
and DQ
29
to DQ
32
output from the output sections
2
h
and
2
d far from the pad
10
, as well as a timing difference between the echo clock signals KQ.
The timing difference as described above may be alleviated by the depicted configuration wherein the internal clock signal CLKT is subjected to buffering by using inverters
4
a
to
4
e
disposed for this purpose to generate CLKT
1
to CLKT
4
which are in phase with the external clock signal CLK.
In this situation, it is important to reduce the timing difference between the echo clock signal KQ
1
to KQ
4
supplied through the echo clock generator
3
a to
3
d
and the read data DQ
1
to DQ
32
supplied through the data output sections
2
a
to
2
h
. This means that the locations of the data output sections
2
a
to
2
h
and the echo clock generators
3
a
to
3
d
are important as viewed from the input pad
10
.
FIG. 3
shows example of the echo clock generators
3
a
to
3
d
and the data output sections
2
a
to
2
h
in a conventional PBSRAM. The echo clock generator designated by numeral
30
includes a delay gate
31
and an output buffer
32
, whereas the data output section designated by numeral
20
includes a data register
21
for latching the data WRB read from a memory cell
23
by a sense amplifier
24
based on the timing of the internal clock signal CLKT, and an output buffer
22
.
The output buffer
22
of the data output section
20
receives data WRB stored in the data register
21
, delivers the read data DQ at a high level of the data control signal OE and stops the read data DQ at a low level of the data control signal OE.
The output buffer
32
of the echo clock generator
30
iteratively outputs the echo clock signal KQ. Thus, the control signal for the output buffer
32
corresponding to the data control signal OE for the output buffer
22
is fixed to the source potential for enabling the output buffer
32
at any time, as shown in FIG.
3
.
The delay gate
31
adjusts the timing of the echo clock signal KQ to be concurrent with the occurrence of the read data. The register
21
includes a master latch and a slave latch cascaded in this order. The data register
21
latches the data WRB at the rising edge of the internal clock signal CLKT and holds therein the data for one clock cycle until the next rising edge of CLKT.
In operation, when a data WRB is latched by the master latch and received in the slave latch of the data register
21
at the rising edge of CLKT,

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