SRAM device and operating method

Details SRAM device and operating method SRAM device and operating method

2006-07-26

2008-09-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S154000

Reexamination Certificate

active

07420854

ABSTRACT:
An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

REFERENCES:
patent: 6442060 (2002-08-01), Leung et al.
patent: 2005/0047196 (2005-03-01), Bhavnagarwala et al.
patent: 2005/0157537 (2005-07-01), Wei et al.

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