SRAM cells having landing pad in contact with upper and...

Details SRAM cells having landing pad in contact with upper and... SRAM cells having landing pad in contact with upper and...

2006-11-14

2006-11-14

Doan, Theresa T. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000

Reexamination Certificate

active

07135746

ABSTRACT:
SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

REFERENCES:
patent: 5001539 (1991-03-01), Inoue et al.
patent: 5612552 (1997-03-01), Owens
patent: 6429484 (2002-08-01), Yu
patent: 2000-114453 (2000-04-01), None
patent: 1020020096743 (2002-12-01), None
patent: 1020040069585 (2004-08-01), None
Office Action from Korean Patent Office for Korean Patent Application No. 10-2004-0090608 mailed May 25, 2006.

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