SRAM cells having inverters and access transistors therein...

Details SRAM cells having inverters and access transistors therein... SRAM cells having inverters and access transistors therein...

2008-05-06

2008-05-06

Harvey, Minsun Oh (Department: 2828)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S067000, C257S350000, C257S798000, C257S331000, C257S328000, C257SE21661, C257S393000, C257S401000

Reexamination Certificate

active

07368788

ABSTRACT:
Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

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