SRAM cell with read buffer controlled for low leakage current

Details SRAM cell with read buffer controlled for low leakage current SRAM cell with read buffer controlled for low leakage current

2011-07-26

2011-07-26

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189060, C365S226000

Reexamination Certificate

active

07986566

ABSTRACT:
A functional memory of the integrated circuit includes row and column periphery units and an array of memory cells having a core storage element and a read buffer. The functional memory further includes a read buffer supply line that is connected to the read buffer, wherein the read buffer supply line is switchable between an operating mode output and a low-power mode output of a read buffer supply that is separate from core storage element supplies.

REFERENCES:
patent: 6563730 (2003-05-01), Poplevine et al.
patent: 7164596 (2007-01-01), Deng et al.
patent: 7193924 (2007-03-01), Ramaraju et al.
patent: 7684274 (2010-03-01), Rengarajan et al.
patent: 2009/0175113 (2009-07-01), Deng et al.

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