SRAM cell with improved layout designs

Details SRAM cell with improved layout designs SRAM cell with improved layout designs

2007-10-09

2007-10-09

Tran, Long K. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S903000, C257SE27098, C257SE21661, C365S189110, C365S154000, C365S156000

Reexamination Certificate

active

11293340

ABSTRACT:
A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-up transistor and a second pull-down transistor serially coupled between the supply source and the complementary supply source. The cell further includes a first pass-gate and second pass-gate transistors coupled to the first and second inverters, respectively. The first pass-gate transistor and the first pull-up transistor are respectively constructed on a first P-type well and a first N-type well adjacent to one another, which are overlaid by a first doped region and a second doped region of substantially the same width in alignment with one another, respectively.

REFERENCES:
patent: 6750555 (2004-06-01), Satomi et al.
patent: 2005/0248977 (2005-11-01), Liaw
patent: 2006/0102957 (2006-05-01), Liaw

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