SRAM cell with horizontal merged devices

Details SRAM cell with horizontal merged devices SRAM cell with horizontal merged devices

2006-03-28

2006-03-28

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189090, C365S189011, C365S154000

Reexamination Certificate

active

07020030

ABSTRACT:
A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (VDIFF) to a selected memory cell by providing a column line potential (VC) and a row line potential (VR). According to this method, VDIFFis increased by an increment less than a transistor threshold voltage (VT). It is then determined whether the increased VDIFFresults in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying VDIFFand increasing VDIFFby an increment more than VTto set the selected memory cell to a one state.

REFERENCES:
patent: 5304502 (1994-04-01), Hanagasaki
patent: 5771196 (1998-06-01), Yang
patent: 5950219 (1999-09-01), Rao
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6128216 (2000-10-01), Noble, Jr. et al.
patent: 6275433 (2001-08-01), Forbes
patent: 6654275 (2003-11-01), Forbes

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