Split gate memory device

Details Split gate memory device Split gate memory device

2005-04-12

2005-04-12

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S314000

Reexamination Certificate

active

06878987

ABSTRACT:
A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.

REFERENCES:
patent: 5879993 (1999-03-01), Chien et al.
patent: 6133097 (2000-10-01), Hsieh et al.
patent: 20020068403 (2002-06-01), Huang
patent: 2001-085544 (2001-03-01), None
patent: 2001-91532 (2001-10-01), None

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