Split gate memory cell method

Details Split gate memory cell method Split gate memory cell method

2006-09-26

2009-08-25

Nguyen, Ha (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S596000

Reexamination Certificate

active

07579243

ABSTRACT:
Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.

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