Split gate flash memory device with source line

Details Split gate flash memory device with source line Split gate flash memory device with source line

2000-08-07

2001-12-04

Pham, Long (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06326662

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) memory devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,103,274 of Tang et al. for “Self-Aligned Source Process and Apparatus” shows a method of forming self-aligning source region EPROM, flash EPROM and EEPROM memory devices.
U.S. Pat. No. 5,120,671 of Tang et al. for “Process for Self-Aligning a Source Region with a Field Oxide Region and a Polysilicon Gate” also shows a method of forming self-aligning source region EPROM, flash EPROM and EEPROM memory devices.
See U.S. Pat. No. 5,656,513 of Wang et al. for “Nonvolatile Memory Cell Formed Using Self-Aligning Source Implant”.
Also see U.S. Pat. No. 5,466,624 of Ong et al. for “Isolation Between Diffusion Lines in a Memory Array”.
SUMMARY OF THE INVENTION
In accordance with this invention, the split gate electrode MOSFET devices comprises a tunnel oxide layer over a semiconductor substrate, a floating gate electrode layer over the tunnel oxide layer, and a pattern of adjacent caps over the floating gate electrode layer. There are adjacent gate electrode stacks formed from the tunnel oxide layer and the floating gate electrode layer in the pattern of the caps. Intermetal dielectric and control gate layers overlie the substrate, covering the stacks. The intermetal dielectric and control gate layers are patterned into adjacent mirror image split gate electrode pairs. Source regions and drain regions are self-aligned with the gate electrode stacks and split gate electrode pairs.
Preferably, the floating gate electrode layer comprises a doped polysilicon layer; and the caps on the surface of the doped polysilicon comprise polysilicon oxide caps.
Preferably, the floating gate electrode layer comprises a doped polysilicon layer; the slots have a width from about 3500 Å to about 6500 Å; and there are caps on the surface of the doped polysilicon formed into polysilicon oxide caps on the surface of the polysilicon layer.
Preferably, FOX regions are formed in the substrate. Active regions are formed in the substrate below the tunnel oxide layer. The floating gate electrode is formed of doped polysilicon layer. The caps on the surface of the doped polysilicon comprise polysilicon oxide caps on the surface of the polysilicon layer. The tunnel oxide layer and the floating gate electrode layer being in the pattern of the cap.
In accordance with another aspect of this invention, a split gate electrode MOSFET devices includes the following. A tunnel oxide layer overlies a semiconductor substrate. A floating gate electrode layer overlies the tunnel oxide layer and a cap overlies the floating gate electrode layer. A gate electrode stack is formed with the tunnel oxide layer and the floating gate electrode layer in the pattern of the cap. There is a source line slot in the center of the gate electrode stack down to the substrate. A source region is formed in the substrate at the base of the source line slot. There are intermetal dielectric and control gate layers overlying the substrate. The intermetal dielectric and control gate layers comprise adjacent mirror image split gate electrode pairs. Source and drain regions are self-aligned with the gate electrode stack and split gate electrodes pairs.
Preferably, the floating gate electrode comprises a doped polysilicon layer. The slot has a width from about 3500 Å to about 6500 Å. The cap on the surface of the doped polysilicon comprises a polysilicon oxide cap.
Preferably, the floating gate electrode comprises a doped polysilicon layer. The cap on the surface of the doped polysilicon comprises a polysilicon oxide cap on the surface of the polysilicon layer. The tunnel oxide layer and the floating gate electrode layer are patterned in the pattern of the cap.
Preferably, a silicon nitride floating gate mask overlies the polysilicon layer.
This invention provides a method for shrinking array dimensions by one mask defining of cell and source line in a split gate flash memory device. Features of the invention include as follows:
1. The shape of field oxide regions begin with rows of long stripes.
2. Cells are defined by the formation of blocks between long field oxide stripes. Then polysilicon and silicon nitride are etched away and polysilicon oxidation caps are formed for split gate flash memory processing.
3. After silicon nitride removal and polysilicon etching, floating gates are formed basically. Then source lines perpendicular to field oxide stripes are defined, which separate blocks of the floating gate electrode stacks. By the etching of polysilicon oxide, polysilicon and field oxide with one mask, floating gates with self-aligned source regions can be formed, which is easy to scale down the desired cell dimensions.
This invention has the advantages as follows:
1. It improves the photolithography process window in the active region definition to solve the problem of pull back in the head of the field oxide region.
2. It solves the encroachment issue in field oxide, which makes it easy to shrink the active area (OD) design rule.
3. It reduces the encroachment issue in floating gates after polysilicon oxidation.


REFERENCES:
patent: 5103274 (1992-04-01), Tang et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5412238 (1995-05-01), Chang
patent: 5466624 (1995-11-01), Ong et al.
patent: 5597751 (1997-01-01), Wang
patent: 5656513 (1997-08-01), Wang et al.
patent: 5940706 (1999-08-01), Sung et al.
patent: 6097059 (2000-08-01), Yamada
patent: 6124609 (2000-09-01), Hsieh et al.
patent: 6188103 (2001-03-01), Hsieh et al.

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