Split-gate flash memory cell and manufacturing method thereof

Details Split-gate flash memory cell and manufacturing method thereof Split-gate flash memory cell and manufacturing method thereof

2002-12-12

2004-03-23

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000

Reexamination Certificate

active

06709925

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a split-gate flash memory cell and manufacturing method thereof; and, more particularly, to a split-gate flash memory cell with a peak floating gate and manufacturing method thereof.
BACKGROUND OF THE INVENTION
The shape and size of different portions of memory cells affects the performance of the memory cells differently. Thus, with the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes for shrinking the size of the cell and, at the same time, improve its performance. The variations include different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drain regions that are aligned to a floating gate or aligned to spacers.
Referring to
FIG. 1
, there is shown a conventional split-gate flash memory cell disclosed in U.S. Pat. No. 5,970,371.
On a substrate
10
with a plurality of active regions, e.g., a source
11
and a drain
13
, already defined, a tunnel oxide layer
20
is formed. A polysilicon layer
30
is next deposited over the tunnel oxide layer
20
. A portion of the polysilicon layer
30
is oxidized by employing a local oxidation of silicon (LOCOS) process to form a LOCOS polyoxide
35
. The LOCOS polyoxide
35
is used as a hard mask to etch the remaining portion of the polysilicon layer
30
not covered by the LOCOS polyoxide
35
. Since the shape of the LOCOS polyoxide
35
is generally rounded even after performing over-etch, the polysilicon layer
30
is modified as a floating gate
30
with a sharp beak
37
. After an inter-gate oxide layer
60
is deposited, a control gate
70
of polisilicon is formed over a portion of the inter-gate oxide layer
60
.
In order to program the split-gate flash memory cell, charges in the source
11
are transferred through the tunnel oxide layer
20
to the floating gate
30
. On the other hand, in order to erase the split-gate flash memory cell, charges in the floating gate
30
are removed through the inter-gate oxide layer
60
to the control gate
70
.
Since, however, the LOCOS polioxide
35
is rounded to form the sharp beak
37
of the floating gate
30
, the thickness of oxide between the floating gate
30
and the control gate
70
is not uniform. Further, since the control gate
70
and the floating gate
30
are formed separately, the control gate
70
dose not cover the floating gate
30
completely to reduce a coupling ratio between the floating gate
30
and the control gate
70
and, therefore, the programming/erasing efficiency of the split-gate flash memory cell is considerably reduced.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a split-gate flash memory cell with a peak floating gate and manufacturing method thereof to improve a coupling ratio between the peak floating gate and the control gate.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a split-gate flash memory cell, the method comprising the steps of:
(a) providing a substrate;
(b) forming a tunnel oxide layer over the substrate;
(c) forming a peak floating gate layer of conducting material over a portion of the tunnel oxide layer, wherein the peak floating gate layer has a peak structure thereon;
(d) coating an inter-gate insulating layer over the peak floating gate layer and the remaining portion of the tunnel oxide layer and spreading a control gate layer of conducting material over the inter-gate insulating layer;
(e) defining a control gate pattern over the control gate layer;
(f) etching down the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer sequentially to the substrate by using the control gate pattern to generate a control gate, a inter-gate insulating region, a peak floating gate and a tunnel oxide region; and
(g) defining a source and a drain adjoining the tunnel oxide region by using a self-align technique.
In accordance with another aspect of the present invention, there is provided a split-gate flash memory cell comprising:
a substrate defined with a source, a drain and a channel region between the source and the drain;
a tunnel oxide region formed over the channel region;
a peak floating gate of conducting material over a portion of the tunnel oxide region, wherein the peak floating gate has a peak structure thereon;
an inter-gate insulating region formed over the peak floating gate and the remaining portion of the tunnel oxide region; and
a control gate of conducting material formed over the inter-gate insulating region,
wherein the control gate, the inter-gate insulating region, the peak floating gate and the tunnel oxide region are defined with a mask which has a same size as the channel region.


REFERENCES:
patent: 6060360 (2000-05-01), Lin et al.
patent: 6380584 (2002-04-01), Ogawa

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