Split gate flash memory cell

Details Split gate flash memory cell Split gate flash memory cell

1999-07-02

2001-05-15

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S266000, C438S589000, C257S265000, C257S322000

Reexamination Certificate

active

06232180

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor flash memory, and more particularly, to a split-gate flash memory.
BACKGROUND OF THE INVENTION
Toward the end of the 1980s, the semiconductor industry developed the electrically erasable PROM (EEPROM). The result was a new generation of memories targeted at the low cost, high density memory market. The term “flash” historically had been used to describe a mode of programming or erasing an entire memory array at one time. The flash memory is programmed by hot electron injection at the drain edge and erased by Fowler-Nordheim tunneling from the floating gate to the source.
Flash memory is classified as non-volatile memory because a memory cell in the flash memory can retain the data stored in the memory cell without periodic refreshing. Most prior art flash memory can store a single bit in a memory cell. In other words, the memory cell can either store a “one” or a “zero”.
Many flash memory manufacturers chose a thin oxide floating gate process to make an electrically erasable PROM. As seen in
FIG. 1
, the basic cell consists of access transistors and a double polysilicon storage cell with a floating polysilicon gate (FG) isolated in silicon dioxide capacitively coupled to a second polysilicon control gate (CG) which is stacked above it. The storage transistor is programmed by Fowler-Nordheim tunneling of electrons through a thin oxide layer between the gate and the drain (D) of the transistor. The thin tunneling oxide generally is about 90 angstroms thick. One difficulty with this structure is that the memory cell may be erased to a negative threshold voltage and the channel between the drain and source will conduct leakage current even when the control gate (CG) is grounded. Furthermore, the prior art memory cell requires a programming current of 400 microamps to 1 milliamp per cell. In practical applications, this requires a very large charge pump to supply enough current.
Another prior art design known as the split gate flash cell is shown in FIG.
2
. The split gate cell eliminates over erase sensitivity because even if the floating gate (FG) is over erased, conduction in the channel requires the biasing of the control gate which is over another portion of the channel between the source and drain. One disadvantage of this design is that the cell size is increased and the manufacture of the cell suffers from alignment sensitivity.
Yet another type of split gate cell utilizes the so-called source-side injection technique which minimizes the channel current during programming and an on-chip pump circuit can be used to provide adequate programming current by using a single power supply. However, there are still several drawbacks in this design. First, the misalignment from the poly1 (the floating gate) and poly2 (the control gate) layers will always make the cell current unsymmetric. In addition, this design results in easy punchthrough and the cell dimension is hard to scale down in size. Second, the erase mechanism will induce electron trapping and reduce endurance performance.
U.S. Pat. No. 5,614,746 to Hong et al., U.S. Pat. No. 5,674,767 to Lee et al., U.S. Pat. No. 5,789,296 to Sung et al., and the references cited therein illustrate these various prior art approaches to the split gate flash memory cell.
What is needed is a new design for a flash memory cell that overcomes the problems noted above.
SUMMARY OF THE INVENTION
A split gate flash memory cell formed in a semiconductor substrate is disclosed. The memory cell comprises: a deep n-well formed in said substrate; a p-well formed in said deep n-well; a select gate structure formed on said p-well, said select gate structure comprising a stack of a gate oxide, a polysilicon layer, and a cap oxide; a tunnel oxide layer formed on said p-well, said tunnel oxide adjacent to said control gate structure; a floating gate formed over said select gate structure and extending over at least a portion of said tunnel oxide layer; a source formed in said p-well, said source formed adjacent to said floating gate; and a drain formed in said p-well, said drain formed adjacent to said select gate structure.


REFERENCES:
patent: 5872036 (1999-02-01), Sheu
patent: 5970341 (1999-10-01), Lin et al.
patent: 6013552 (2000-01-01), Oyama
patent: 6093608 (2000-07-01), Lin et al.

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