Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-18
2003-02-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06524915
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 2001-9325, filed on Feb. 23, 2001, the contents of which are hereby incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a split-gate flash memory and a method of manufacturing the same.
2. Description of Related Art
Recently split-gate flash memories have found wide use as data storage elements.
FIG. 1
is a top plan view illustrating a structure of a conventional split-gate flash memory.
FIGS. 2A
to
2
J are cross-sectional views taken along line A-A′ of
FIG. 1
, and
FIGS. 3A
to
3
J are cross-sectional views taken along line B-B′ of FIG.
1
.
A method of manufacturing the conventional split-gate flash memory is now explained in detail with reference to
FIGS. 1
,
2
A to
2
J and
3
A to
3
J. Referring to
FIGS. 2A and 3A
, a first oxidation film
101
is formed on an active region of a semiconductor substrate
100
. A first conductive layer
102
is provided on the first oxidation film
101
to form a field oxidation film
103
on a field region of the semiconductor substrate
100
. Preferably, the field oxidation film
103
comprises polycrystalline silicon. The field oxidation film
103
may be formed, for example, using a local oxidation of silicon (LOCOS) process, a poly-buffered local oxidation of silicon (PBL) process, or a shallow-trench isolation (STI) process. The field oxidation film
103
of
FIG. 3A
is formed by the STI process.
In greater detail, the first oxidation film
101
and the first conductive layer
102
are sequentially deposited on the entire surface of the semiconductor substrate
100
. A first nitride layer (not shown) is deposited on the first conductive layer
102
. The first oxidation film
101
, the first conductive layer
102
and the first nitride layer are patterned through a photolithography process to expose a portion of the semiconductor substrate corresponding to the field region. The exposed portion of the semiconductor substrate
100
is etched to form a trench (not shown). Thereafter, an oxidation film is deposited on the first nitride layer comprising the trench, and then a chemical-mechanical polish (CMP) process is performed until the first nitride layer is exposed. The oxidation film is then filled in the trench to form the field oxidation film
103
. The first nitride layer remaining on the first conductive layer
102
is removed. After forming the field oxidation film
103
, a second nitride layer
104
is deposited on the first conductive layer
102
and is patterned to expose a portion of the first conductive layer
102
.
Referring to
FIGS. 2B and 3B
, a second oxidation film
105
is deposited over the whole surface of the semiconductor substrate
100
and covers the second nitride layer
104
and the exposed surface of the first conductive layer
102
. Even though not shown, before depositing the second oxidation film
105
, the first conductive layer
102
is etched using the second nitride layer
104
as a mask, or the exposed portion of the first conductive layer
102
is oxidized by an oxidation process, so that the exposed portion of the first conductive layer
102
is relatively thinner than the non-exposed portion thereof.
As shown in
FIGS. 2C and 3C
, the second oxidation film
105
is etched back to form an oxidation spacer
106
on a side wall of the second nitride layer
104
. Then, using the oxidation spacer
106
as a mask, the exposed portions of the first oxidation film
101
and the first conductive layer
102
, that are not covered with the oxidation spacer
106
and the second nitride layer
104
, are etched to expose a corresponding portion of the semiconductor substrate
100
. Using the oxidation spacer
106
and the second nitride layer
104
as a mask, impurities having a reverse conductivity to that of the semiconductor substrate
100
are ion-implanted into the exposed portion of the semiconductor substrate
100
to form a source junction region
107
.
At this point, even though not shown, a side portion of the first conductive layer
102
is exposed while the first oxidation film
101
and the first conductive layer
102
are etched using the spacer
106
as a mask. In order to prevent a short circuit between the exposed side portion of the first conductive layer
102
and a source line that will be formed in a subsequent process, an oxidation film is deposited over the whole surface of the semiconductor substrate
100
by a chemical vapor deposition (CVD) technique and then is etched back to finally form the oxidation spacer
106
having a structure that surrounds the first conductive layer
102
as shown in FIG.
2
C. Instead of the CVD process, a thermal oxidization process may be used to form the oxidation film.
Subsequently, as shown in
FIGS. 2D and 3D
, a second conductive layer is deposited over the whole surface of the semiconductor substrate
100
and is etched back to form the source line
109
that directly contacts the source junction region
107
. At this point, the source line
109
is insulated from the first conductive layer
102
by the oxidation spacer
106
.
As shown in
FIGS. 2E and 3E
, the second nitride layer
104
is selectively removed using, e.g., a phosphoric acid, and then the first oxidation film
101
and the first conductive layer
102
are etched using the oxidation spacer
106
as a mask to form a first gate insulating layer
110
and a floating gate
111
.
As shown in
FIGS. 2F and 3F
, a third oxidation film
113
and a third conductive layer
114
are sequentially deposited over the whole surface of the semiconductor substrate
100
. Preferably, the third conductive layer
114
is made of polycrystalline silicon. Thereafter, as shown in
FIGS. 2G and 3G
, the third oxidation film
113
and the third conductive layer
114
are simultaneously etched back to form a second gate insulating layer
115
and the word line
116
on a side wall of the oxidation spacer
106
.
Subsequently, as shown
FIGS. 2H and 3H
, a fourth oxidation film and a third nitride layer are deposited over the whole surface of the semiconductor substrate
100
and then are etched back to form a buffer layer
117
and a spacer
118
on a side wall of the word line
116
and to expose a portion of the semiconductor substrate
100
corresponding to a drain junction region that will be formed in a subsequent process. Preferably, the spacer
118
comprises nitride.
As shown in
FIGS. 2I and 3I
, impurities having the same conductivity as that of the source junction region are ion-implanted into the exposed portion of the semiconductor substrate
100
using a mask (not shown) for an ion implantation to form the drain junction region
119
.
Subsequently, as shown in
FIGS. 2J and 3J
, silicide layers
120
are formed on the source line
109
, the drain junction region
119
and the word line
116
through a silicidation process. An interlayer insulator
121
is formed over the whole surface of the semiconductor substrate
100
and a contact hole
122
is formed to expose the drain region
119
. The interlayer insulator
121
includes a contact hole
122
formed at a portion of the drain junction region
119
. Finally, a metal line
123
is formed on the interlayer insulator
121
to contact the drain junction region
119
through the contract hole
122
. Therefore, the conventional split-gate flash memory is completed.
A programming operation and an erasing operation of the conventional split-gate flash memory are explained below.
First, a programming operation of the conventional split-gate flash memory is as follows. As shown in
FIG. 4A
, a high voltage VDD is applied to the source junction region
107
through the source line
109
, and a low voltage 0V is applied to the drain junction region
119
. Electrons generated from the drain junction region
119
move toward the source junction region
107
through a channel region that is weakly inverted by a threshold voltage Vth applied to the word line
116
. The electr
Cho Min Soo
Kim Dong Jun
Lee Young Kyu
Ryu Eui Youl
Le Thao P
Mills & Onello LLP
Nelms David
LandOfFree
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