Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-16
2002-10-22
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S211000
Reexamination Certificate
active
06468863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to split gate field effect transistor (FET) devices with enhanced properties, as employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having formed therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device employed within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an inter-gate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce or reduce charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within non-volatile semiconductor integrated circuit microelectronic fabrications split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to enhanced data retention properties and enhanced programming speed properties.
It is thus towards the goal of providing for use within semiconductor integrated circuit microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic memory fabrications, split gate field effect transistor (FET) devices with enhanced properties, such as but not limited to enhanced data retention properties and enhanced programming speed properties, that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic fabrications, associated semiconductor integrated circuit microelectronic devices formed therein, methods for fabrication thereof and methods for operation thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
For example, Sung et al., in U.S. Pat. No. 6,005,809, discloses a method for programming within a semiconductor integrated circuit microelectronic fabrication a split gate field effect transistor (FET) device with enhanced programming speed and a method for erasing within the semiconductor integrated circuit microelectronic fabrication the split gate field effect transistor (FET) device with enhanced erasing speed, while simultaneously enhancing a cycling endurance of the split gate field effect transistor (FET) device. To realize the enhanced programming speed, the programming method employs applying within the split gate field effect transistor (FET) device a simultaneous first positive voltage to a control gate, a first moderately negative voltage to a semiconductor substrate and a first slightly positive voltage to a drain region in order to establish a constant programming current, and then applying a second positive voltage to a source region for programming purposes. Similarly, to realize the enhanced erasing speed, the erasing method employs applying within the split gate field effect transistor (FET) device a large positive voltage to the control gate, the first moderately negative voltage to the semiconductor substrate and a second moderately negative voltage to the source region.
In addition, Chang, in U.S. Pat. No. 6,043,530, discloses an electrically erasable programmable read only memory (EEPROM) device that may be both programmed and read while employing low currents for both programming operations and erasing operations. The electrically erasable programmable read only memory (EEPROM) device is fabricated with a structure generally analogous with a stacked gate field effect transistor (FET) device, but with a control gate of width less than a floating gate width and centered within the floating gate width, and further wherein there is employed adjacent both the floating gate and the control gate, but spaced further from the control gate than the floating gate, a polysilicon sidewall spacer employed as an erasing gate.
Finally, Lin et al., in U.S. Pat. No. 6,046,086, discloses a split gate field effect transistor (FET) device, and a method for fabricating the split field effect transistor (FET) device, wherein the split gate field effect transistor (FET) device has enhanced data retention properties and enhanced capacitive coupling properties. To realize the foregoing objects, the split gate field effect
Chang Chuan-Li
Chu Wen-Ting
Hsieh Chia-Ta
Kuo Di-Son
Tsaur Sheng-Wei
Magee Thomas
Taiwan Semiconductor Manufacturing Co. Ltd
Thomas Tom
Tung & Associates
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