Split computer architecture to separate user and processor...

Details Split computer architecture to separate user and processor... Split computer architecture to separate user and processor...

2002-05-20

2004-10-19

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C710S065000, C710S120000, C710S120000

Reexamination Certificate

active

06807639

ABSTRACT:

BACKGROUND
FIELD OF THE INVENTION
This invention relates to computer networking systems.
BACKGROUND AND SUMMARY OF THE INVENTION
U.S. application Ser. No. 09/430,162 describes a computer paradigm providing remarkable advantages in computer networking. In particular, the so-called split computer separates the CPU and applications programs from a computer's local controllers and peripherals, such that the CPU and applications may be stored and maintained at a central facility convenient to a facilities manager, while local controllers can remain at the desktop with the associated user peripherals. The specific advantages and general aspects of this new paradigm is described in more detail in the above described U.S. application which is incorporated herein by reference and for sake of brevity will not be repeated herein.
FIG. 24
illustrates an example embodiment of the so-called split computer. As shown in
FIG. 24
, the remote target room
185
contains a number of targets having CPUs, hard drives, etc. One target
186
is shown connected to a work station
188
via twisted pair
187
. The target
186
is also referred to as the host side
186
and the work station
188
is also referred to as the remote side
188
. On the host side
186
, the CPU
189
communicates on a host bus
190
. The host bus
190
can be a standard PCI bus within a CPU motherboard, or can be any other type of computer data bus. On the remote side
188
, a remote bus
193
communicates with various local controllers
194
which will be described in greater detail following. Among other functions, the local controllers
194
support various peripherals
195
located at the work station
188
. As one can see from
FIG. 24
, in effect, the bus that would ordinarily carry communications from CPU
189
to controllers
194
has been “split” into buses
190
and
193
communicating with each other via interfacing
191
and
192
and twisted pair (or other communications line/media)
187
.
The practical result of the split computer is that the host bus
190
and remote bus
193
must be interfaced such that the CPU
189
can engage in normal communications with the local controllers
194
. Ideally, the host bus
190
and remote bus
193
will be capable of communications along a large range of distances including a few feet, as far as one corner of a building to another, and even greater distances if necessary. The present invention is not limited to any particular kind of communication line type such as wire line, fiber optic, air wave, etc., but it would be particularly advantageous if the present invention allowed the host bus
190
to communicate with the remote bus
193
over long distances via commonly available twisted pair
187
. For this purpose, special interfacing
191
and
192
must be provided between the host bus
190
and remote bus
193
at the host side
186
and remote side
188
.
Some schemes already exist for communication along a computer bus and between plural computer buses. Examples of these prior art interfaces are shown and described with respect to
FIGS. 1-3
. Thus, as shown in
FIG. 2
, a PCI type bus
12
may include a number of components communicating along the bus
12
in accordance with the standard PCI local bus specifications. The PCI local bus specifications are standards by which computer communications can occur within internal buses of a PC-based computer. The PCI local bus specification rev. 2.1, dated Jun. 1, 1995, is an example prior art PCI bus specification and is incorporated herein by reference. In
FIG. 2
, the PCI bus
12
provides communication between a master
14
and one or more targets
15
A-
15
B. Communications occur when the master
14
provides information addressed to a particular targets
15
A-
15
B and places that communication on the PCI bus
12
. Such communications along PCI buses
12
are not uncommon.
The timing of communications between a master
14
and targets
15
A-
15
B is traditionally specified in the bus specification. Thus, the PCI bus specification or PCI bus
12
provides hard limits on how much time can elapse before a command issued by master
14
“times out” without receiving response. In other words, master
14
may send a command to targets
15
A-
15
B on PCI bus
12
with an address for target
15
A to perform a particular operation. The target
15
A must receive the command and respond to the command within a certain time set by the PCI standard before the master
14
will time out on the issued command.
Thus, as shown in
FIG. 2
, master
14
issues a command at clock C
0
to target
15
B. Target
15
B will operate on the command and return a response (or acknowledgment) to master
14
, which will be received by master
14
no later than C
0
+X where X is a number of clocks dictated by the bus standard. If C
0
+X exceeds the PCI standard for response time to a command, master
14
will time out on the command before it receives its response from target
15
B. This situation is rarely, if ever, a design constant for a typical PCI system but it does limit the physical size of a PCI bus and has application to the present invention, as will be described.
The time out aspects of bus communications pose a problem in the split computer paradigm. Referring again to
FIG. 24
, assuming CPU
189
to be a client speaking on host bus
190
, the CPU
189
will be sending commands to local controller
194
via the path (in order): host bus
190
, interface
191
, twisted pair
198
, interface
192
, and remote bus
193
. Unfortunately, this distance of travel precludes the local controller
194
from operating on the command and responding to the CPU
189
in time before the CPU
189
times out on the command. In other words, the standard bus time out restrictions are too small for transmission response to occur from CPU
189
to local controllers
194
and back to CPU
189
before the time out occurs.
FIG. 1
illustrates a prior art arrangement which addresses communication between plural PCI buses
12
and
13
. In the embodiment of
FIG. 1
, bridge
10
allows an increased number of masters/targets on a PCI system by connecting a first bus with a second bus to provide a second set of loads. The bridge
10
is a known device and may be, for example, a Digital Semiconductor PCI-to-PCI bridge. An example of such a bridge is the Digital Semiconductor 21152 bridge, described in Digital Semiconductor's February 1996 data sheet, which is incorporated herein by reference.
As shown in
FIG. 3
, the bridge
10
assists the clients
14
/
16
and targets
15
A-B/
17
A-B to communicate with each other over the PCI buses
12
and
13
. Thus, a master
14
communicates differently to targets
15
A-B than it would to targets
17
A-B. In the former case, if master
14
desires to read a memory location of target
15
A, master
14
simply sends an address to target
15
A on PCI bus
12
and target
15
A acknowledges the request to master
14
on the PCI bus
12
, before the time out condition occurs (and can then return the data). In the latter case, however, the target
17
A cannot receive and return the information requested before master
14
will time out. Thus, the master
14
sends its read request to bridge
10
on PCI bus
12
. The bridge returns an instruction to master
14
instructing the master
14
in essence “sorry, try again later.” Meanwhile, however, bridge
10
sends the read request to the target
17
A on PCI bus
13
. As the master
14
continues asking the bridge
10
for the read request and the bridge
10
continues to tell the master
14
“try again,” the target
17
A is retrieving the requested data from its memory. Once the target
17
A has retrieved the requested data, it puts it on PCI bus
13
to bridge
10
. In the next instance in which master
14
sends the read request to bridge
10
, the bridge
10
responds within the time out period with the requested information previously sent to it by the target
17
A.
The prior art arrangement of
FIG. 3
cannot be simply substituted into the split computer envi

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