Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-05-16
2000-09-26
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438304, 438305, 438596, H01L 21336
Patent
active
061241741
ABSTRACT:
A semiconductor process includes forming a spacer support structure on an upper surface of a semiconductor substrate. The semiconductor substrate includes a channel region that is laterally displaced between first and second source/drain regions. A. The spacer support structure includes a substantially vertical sidewall that is laterally aligned over a boundary between the first source/drain region and the channel region of the semiconductor substrate. A gate dielectric is then grown and a transistor gate fabricated by forming a first spacer structure on the sidewall of the spacer support structure. The first spacer structure includes a substantially vertical first sidewall in contact with the spacer support structure sidewall and further includes a second sidewall that is laterally aligned over a boundary between the channel region and the second source/drain region of the semiconductor substrate. The spacer support structure is then removed and source/drain impurity distributions are introduced into the source/drain regions of the semiconductor substrate.
REFERENCES:
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4442589 (1984-04-01), Doo et al.
patent: 4460413 (1984-07-01), Hirata et al.
patent: 4597827 (1986-07-01), Nishitani et al.
patent: 5041895 (1991-08-01), Contiero et al.
patent: 5202272 (1993-04-01), Hsieh et al.
patent: 5283449 (1994-02-01), Ooka
patent: 5373476 (1994-12-01), Jeon
patent: 5445107 (1995-08-01), Roth et al.
patent: 5468666 (1995-11-01), Chapman
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5679971 (1997-10-01), Tamba et al.
XP000671026 IBM Technical Disclosure, vol. 30, No. 3, Aug. 1987, pp. 1136-1137.
XP000120044 IBM Technical Disclosure, vol. 33, No. 1A, Jun. 1990, pp. 75-77.
International Search Report for PCT/US 98/06889 mailed Jul. 29, 1998.
Gardner Mark I.
Spikes Thomas E.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Trinh Michael
LandOfFree
Spacer structure as transistor gate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Spacer structure as transistor gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Spacer structure as transistor gate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2099468