Spacer process to eliminate corner transistor device

Details Spacer process to eliminate corner transistor device Spacer process to eliminate corner transistor device

1999-11-02

2001-03-27

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S297000, C438S424000, C438S437000

Reexamination Certificate

active

06207513

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to a method for eliminating parasitic corner devices which form at corners of active areas in semiconductor devices and more particularly, to a method for forming an isolation spacer for increasing a threshold voltage for the parasitic corner devices.
2. Description of the Related Art
Field effect transistors (FET) for semiconductor devices typically include a doped active area
10
where a channel
14
forms between a source
8
and a drain
12
of the FET as shown in
FIGS. 1A and 1B
. When a gate electrode
12
is activated under proper conditions, conduction of current between source and drain occurs through a channel
14
(shown in phantom lines) below the gate electrode
12
. Many transistor designs include an active area which is at a different height relative to isolation regions
16
adjacent to the active area
10
. Due to process control, these isolation regions
16
may be lower or higher than active area
10
.
Due to the height difference between the active areas
10
and the adjacent isolation regions
12
, parasitic corner devices
18
are formed between the corners of the active areas and a portion of the gate conductor formed in a divot
20
adjacent to the corners. The divot
20
is created during the formation removal of a silicon nitride liner
22
formed in shallow trenches adjacent to the active areas
10
. When a gate oxide
24
is formed the divot
20
remains and fills with polysilicon of the gate electrode
12
. This parasitic leakage due to the corner device reduces FET performance and leads to errors in data or malfunctions in the FET.
Therefore, a need exists for a spacer which fills the divot to prevent the gate conductor from entering the divot. A further need exists for such a spacer to be formed after implantation of active areas to further reduce a threshold voltage of parasitic corner devices.
SUMMARY OF THE INVENTION
A method for forming spacers for preventing formation of parasitic corner devices in transistors, in accordance with the present invention, includes etching trenches into a semiconductor substrate to form an active area region, lining the trenches and the active area region with a first dielectric material and forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material. The first dielectric material is removed from the active area region, and a gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the transistor. After the step of implanting, a spacer layer is formed from a third dielectric material over the gate oxide layer to fill the divots followed by anisotropically etching the spacer layer to form spacers in the divots such that gate conductor material is prevented from entering the divots, and the gate conductor material is spaced apart from corners of the active area region by the spacers to prevent the formation of the parasitic corner devices.
A method for forming a dielectric spacers for preventing formation of parasitic corner devices in field effect transistors includes the steps of etching trenches into a silicon substrate to form an active area region, lining the trenches and the active area region with silicon nitride, forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a silicon dioxide, and removing the silicon nitride from the active area region. A gate oxide is formed over the active area region wherein divots form between the active area region and the shallow trench isolation regions. Dopants are implanted into the active area region to form a source and drain of the field effect transistor. After the step of implanting, a spacer layer is formed from a third dielectric material over the gate oxide layer to fill the divots followed by anisotropically etching the spacer layer to form spacers in the divots such that gate conductor material is prevented from entering the divots, and the gate conductor material is spaced apart from corners of the active area region by the spacers to prevent the formation of the parasitic corner devices.
In alternate methods, the third dielectric material may be selectively etched relative to the gate oxide. The third dielectric material may include a nitride or an oxide. The third dielectric material may be deposited by a chemical vapor deposition process. The first dielectric material may include silicon nitride. The second dielectric material may include silicon oxide. The step of forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material may include the step of forming shallow trench isolation regions adjacent to the active area region such that the active area region is disposed above a top surface of the second dielectric material. The step of forming shallow trench isolation regions adjacent to the active area region by filling the trenches with a second dielectric material may include the step of forming shallow trench isolation regions adjacent to the active area region such that the active area region is disposed below a top surface of the second dielectric material. The trenches may be filled with silicon dioxide. The spacer layer may include a thickness of approximately 1-3% of a width of the active area region.


REFERENCES:
patent: 5436190 (1995-07-01), Yang et al.
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5899727 (1999-05-01), Hause et al.
patent: 5923991 (1999-07-01), Bronner et al.

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