Spacer formation in a deep trench memory cell

Details Spacer formation in a deep trench memory cell Spacer formation in a deep trench memory cell

2002-01-17

2003-07-08

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000

Reexamination Certificate

active

06589832

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to a trench DRAM memory cell and more specifically to a process for forming a nitride spacer used during the manufacture of the trench which avoids the formation of nitride filaments over the trench, thereby preventing the creation of shorts due to voids being filled with gate poly.
BACKGROUND OF THE INVENTION
The primary driving motivator in commercial memory cells and architecture is the desire to pack more memory capability into a smaller integrated circuit. This goal necessarily involves competing trade-offs in cost, circuit complexity, power dissipation, yield, performance, and the like. Trench capacitors are known in the art as an architecture whereby the overall size (in terms of surface area or chip “real estate”) of the memory cell is reduced. The size reduction is accomplished by forming the capacitor of the memory cell in a trench.
As is known in the art, a typical DRAM cell includes a capacitor upon which is stored a charge (or no charge depending upon the cell's state) and a pass transistor, which is used to charge the capacitor during writing and in the read process to pass the charge on the capacitor to a sense amplifier.
In most recent manufacturing, planar transistors are used for the pass transistors. Such planar transistors have a critical dimension of gate length that is typically 110 nm or greater. Below that size, the transistor performance becomes degraded and is very sensitive to process tolerances. As such, for DRAM cells that are desired to be shrunk below a roughly 110 nm ground rule, existing planar transistors cannot provide the performance necessary for proper DRAM cell operation. A need exists, therefore, for a DRAM memory cell employing a pass transistor architecture that maintains acceptable performance even when shrunk to very small dimensions. Deep trench memory cells represent one approach to meet this challenge.
A method of manufacturing deep trench memory cell comprises: forming a buried plate within a semiconductor substrate, forming a deep trench having sidewalls within an active area of a semiconductor substrate, forming an oxide along the sidewalls of the deep trench, and forming a trench collar along a lower portion of the deep trench. The method further comprises filling the trench partly with polysilicon, wherein the polysilicon is outdiffused into the active area from the trench in those portions not bound by the trench collar during subsequent processing steps. The method also comprises forming a trench top oxide on the polysilicon, filling the trench with a gate polysilicon above the trench top oxide, forming a first doped region adjacent one sidewall of the trench and a second doped region adjacent another sidewall of the trench. These steps are followed by forming a contact to the gate polysilicon and connecting the gate polysilicon to a word line, and forming a contact to the first and second doped regions and connecting the first and second doped regions to a bit line.
The method also provides for forming the capacitor of the memory circuit being formed in a lower portion of a trench, and further comprises a logical pass transistor having a vertical gate formed within an upper portion of the trench, along with a source region, a drain region, and a gate with a gate oxide adjacent the source and drain regions.
SUMMARY OF THE INVENTION
Present techniques of forming a nitride spacer often produced devices with shorts resulting from nitride filament overhangs which cause voids in the spacer. The shorts occur when the spacer voids are subsequently filled with the conductive poly. According to the present invention, this problem is avoided in a process for manufacturing deep trench memory cells in a substrate covered by a pad nitride layer with a top surface and a bottom surface, and wherein the top surface in turn is covered by an oxide layer. Deep trench memory cells typically include a polysilicon gate (or sometimes referred to as a poly gate) which fills the trench to a level above a trench collar oxide. Then, according to the process steps of the invention, polysilicon (or poly) is deposited so as to cover the nitride layer and to underfill the trench so as to leave an open core extending from the top surface of the nitride layer into the trench. An oxide fill process is then used to fill the open core and cover the poly. The oxide fill and the poly it covers are then removed or etched down to the top surface of the pad nitride layer leaving an area of poly with an oxide core. The poly is then recessed and a nitride layer is deposited to form the nitride spacer. The oxide core is then stripped away to again leave an open core in the poly. The aperture or open core is then filled with a poly stud which extends from the gate poly to a level above the top surface of the pad nitride spacer. The combination structure is then subjected to a wet RTP (Rapid Thermal Processing) oxidation process to strip off the nitride layer.


REFERENCES:
patent: 2002/0155654 (2002-10-01), Dyer et al.

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