Spacer assisted trench top isolation for vertical DRAM's

Details Spacer assisted trench top isolation for vertical DRAM's Spacer assisted trench top isolation for vertical DRAM's

2002-04-18

2003-07-01

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S247000, C438S249000, C438S386000, C438S387000

Reexamination Certificate

active

06586300

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of integrated circuits (IC's), and more particularly to the fabrication of memory IC's.
BACKGROUND
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and a common type of semiconductor memory is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells arranged in an array, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
DRAM storage capacitors are typically formed by etching deep trenches in a semiconductor substrate, and depositing and patterning a plurality of layers of conductive and insulating materials over the substrate in order to produce a storage capacitor that is adapted to store data, represented by a one or zero. Prior art DRAM designs typically comprise an access FET disposed in a subsequently deposited layer, disposed above and to the side of the storage capacitor.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. Decreasing the size of DRAM's creates manufacturing challenges.
More recent DRAM designs involve disposing the access FET directly above the storage capacitor, sometimes referred to as a vertical DRAM, which saves space by conserving surface area, and results in the ability to place more DRAM cells on a single chip. In vertical DRAM technology, the isolation layer between the deep trench (DT) fill and the vertical gate oxide in the upper part of the deep trench is often referred to as trench top oxide (TTO).
It is desirable for trench top oxide to have a very well controlled thickness. If the trench top oxide is too thin, shorts or reliability failures in the memory cell will occur. If the trench top oxide is too thick, the buried strap (BS) out-diffusion cannot bridge the trench top oxide, resulting in the loss of device overlap.
What is needed in the art is process of forming trench top isolation for vertical DRAM's that results in the trench top isolation having a well-controlled thickness.
SUMMARY OF THE INVENTION
Embodiments of the present invention achieve technical advantages as a novel trench top isolation layer for a vertical DRAM device, and a method of forming thereof.
In one embodiment, a vertical DRAM device is disclosed. The device includes a workpiece that comprises a semiconductor substrate, a plurality of trenches formed in the workpiece, and a plurality of trench capacitors formed in the trench bottom portion. The capacitors include a buried strap in the outer region and a capacitor inner plate in the inner region. The vertical DRAM device includes a trench top isolation (TTI) layer formed over the trench capacitors in the trench top portion, wherein the trench top isolation layer has a greater thickness over the capacitor inner region than over the capacitor outer region.
Also disclosed is a method of forming a trench top isolation layer of a vertical DRAM device. The method includes providing a workpiece, the workpiece comprising a substrate having a plurality of trenches formed therein, wherein a trench capacitor is formed in each trench bottom portion. The method includes forming a TTI layer in the trench top portion over the trench capacitors, wherein the trench top isolation layer has a greater thickness over the capacitor inner region than over the capacitor outer region.
Further disclosed is method of manufacturing a vertical DRAM device. The method includes providing a workpiece, forming a plurality of trenches in the workpiece, forming a trench capacitor in each trench bottom portion, and disposing a first assist layer over at least the trench sidewalls and trench capacitor top surfaces. A second assist layer is disposed over the first assist layer, the second assist layer is removed from over at least the trench capacitor top surface, and the first assist layer is removed from at least the trench capacitor top surface using the second assist layer as a mask, leaving a portion of the workpiece at the trench sidewalls exposed proximate the trench capacitor top surface. The method includes removing the second assist layer, disposing a first insulating layer over at least the first assist layer and the trench capacitor top surface, the first insulating layer being conformal, and disposing a second insulating layer over the first insulating layer. The second insulating layer is removed from at least the trench sidewalls, leaving a portion of the second insulating layer over the trench capacitor top surface, and the first insulating layer and the first assist layer are removed from the trench sidewalls, leaving a portion of the first insulating layer disposed over the trench capacitor top surface. The remaining portions of the first and second insulating layer form a TTI layer of the vertical DRAM device.
A method of processing a semiconductor device that includes at least one trench formed within a workpiece is further disclosed. The method includes forming a first component within a bottom portion of the trench, leaving an upper portion of the trench exposed, and forming a first sacrificial oxide over at least the trench sidewalls and the first component top surface. A first assist layer is disposed over the first sacrificial oxide, wherein the first assist layer comprises a semiconductor material. A second assist layer is disposed over the first assist layer, wherein the second assist layer comprises an oxide. The second assist layer is removed from at least over the first component top surface, leaving portions of the second assist layer remaining over the trench sidewalls. The second assist layer is used as a mask to remove the first assist layer from at least over the first component top surface, leaving the first assist layer over at least a portion of the trench sidewalls. The second assist layer is removed from the trench sidewalls, and a first insulating material is deposited over the first assist layer and the first component top surface, wherein the first insulating material comprises a nitride. A second insulating material is deposited over the first insulating material, wherein the second insulating material comprises an oxide. The method includes removing the second insulating material from at least the trench sidewalls, and removing the first insulating material and first assist layer from a top portion of the trench sidewalls, wherein the second insulating material and first insulating material remaining over the first component comprise a TTI layer.
Advantages of embodiments of the invention include providing a TTI layer and method of forming thereof, wherein the TTI layer has a well-controlled thickness. The TTI layer is thicker over the inner region of the underlying storage capacitor, improving the insulative properties of the TTI layer in the central region. The TTI layer is thinner over the outer region of the storage capacitor, which improves the source diffusion across the TTI layer. In addition, the TTI layer formation is self-aligned. Furthermore, the process allows the ability to implant dopants into the workpiece prior to forming the TTI layer, providing TTI layer extension diffusion.


REFERENCES:
patent: 5641694 (1997-06-01), Kenney
patent: 6074909 (2000-06-01), Gruening
patent: 6110792 (2000-08-01), Bronner et al.
patent: 6225158 (2001-05-01), Furukawa et al.
patent: 6255683 (2001-07-01), Radens et al.
patent: 6352892 (2002-03-

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