Source line fabrication process for flash memory

Details Source line fabrication process for flash memory Source line fabrication process for flash memory

1999-01-05

2000-06-06

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438529, H01L 218247

Patent

active

060717793

ABSTRACT:
A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52). The first photomask (100) may expose a strip region (102) of the semiconductor substrate (52) and the isolation structure (70). The isolation dielectric material (78) may be removed from the exposed portion the isolation structure (70) to expose the semiconductor substrate (52). A dopant may be implanted into the exposed semiconductor substrate (52) to form the source line (24) in the semiconductor device.

REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 5418741 (1995-05-01), Gill
patent: 5506160 (1996-04-01), Chang
patent: 5763309 (1998-06-01), Chang

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