Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-28
2009-08-11
Garber, Charles D. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S274000, C438S300000, C438S301000, C438S303000, C438S305000, C257SE21177, C257SE21290
Reexamination Certificate
active
07572706
ABSTRACT:
A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.
REFERENCES:
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6833307 (2004-12-01), Wristers et al.
patent: 2005/0067662 (2005-03-01), Lee et al.
patent: 2005/0275021 (2005-12-01), Matsumoto et al.
patent: 2007/0034906 (2007-02-01), Wang et al.
patent: 2007/0235817 (2007-10-01), Wang et al.
patent: 2007/0298557 (2007-12-01), Nieh et al.
patent: 2007/0298565 (2007-12-01), Nieh et al.
patent: 2008/0102573 (2008-05-01), Liang et al.
Hortsmann et al; “Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies”; Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International Dec. 5-7, 2005 pp. 233-236.
PCT Search report and Written Opinion for corresponding PCT Application No. PCT/US08/53563 mailed May 30, 2008.
Winstead Brian A.
Zhang Da
Ahmadi Mohsen
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Garber Charles D.
Singh Ranjeev K.
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