Source/drain extension implant process for use with short...

Details Source/drain extension implant process for use with short... Source/drain extension implant process for use with short...

2007-11-20

2007-11-20

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S514000, C257SE21598

Reexamination Certificate

active

10842308

ABSTRACT:
The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

REFERENCES:
patent: 5486712 (1996-01-01), Arima
patent: 6187643 (2001-02-01), Borland
patent: 6297098 (2001-10-01), Lin et al.
patent: 2004/0137687 (2004-07-01), Feudel et al.

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