Source drain and extension dopant concentration

Details Source drain and extension dopant concentration Source drain and extension dopant concentration

2002-12-10

2004-11-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S231000, C438S287000

Reexamination Certificate

active

06812073

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices and, more particularly, to improving source drain and extension dopant concentration.
BACKGROUND OF THE INVENTION
During the fabrication of certain types of semiconductor devices, extension and source drain regions may be sequentially implanted on either side of a gate stack formed on the surface of a semiconductor substrate. The area of the semiconductor substrate that lies between opposing source drain and source drain extension regions is a channel region. The source drain and source drain extension regions include a high concentration of dopant. High temperature processes, such as annealing, however, may cause the lateral migration of dopant species within the source drain and source drain extension regions and reduce the length of the channel region or otherwise degrade the performance of the device. Typically, the amount of lateral migration is proportional to junction depth of the source drain regions and may be approximately sixty percent of the junction depth.
Spacer layers can mask portions of the semiconductor device during formation of doped regions. Conventional methods of forming the spacer layers, however, often lead to dopant loss and degradation of a doped semiconductor gate and/or doped drain and source drain extension regions. Dopant loss and degradation can lead to an increase in sheet resistance and a lower semiconductor device drive current.
SUMMARY OF EXAMPLE EMBODIMENTS
In accordance with the present invention, disadvantages and problems associated with methods of forming spacer layers are reduced or eliminated.
According to one embodiment of the present invention, a method for forming a semiconductor device is disclosed which includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a short heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
Depending on the specific features implemented, particular embodiments of the present invention may exhibit some, none, or all of the following technical advantages. A technical advantage of one exemplary embodiment of the present invention is that dopant loss and deactivation in the gate and/or drain and extension areas of a semiconductor device may be minimized. Another technical advantage is that transistor drive current may be improved. Additionally or alternatively, the gate to substrate capacitance of the semiconductor device may be improved. Accordingly, the resulting semiconductor device will be more reliable and operate in a more efficient manner.
Other technical advantages may be readily apparent to one skilled in the art from the figures, descriptions and claims included herein. None, some, or all of the examples may provide technical advantages.


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