SONOS memory with inversion bit-lines

Details SONOS memory with inversion bit-lines SONOS memory with inversion bit-lines

2006-12-19

2006-12-19

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S321000, C257S322000, C257S324000, C257S330000, C257S401000, C365S185150, C365S185280, C365S185330

Reexamination Certificate

active

07151293

ABSTRACT:
A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

REFERENCES:
patent: 6555866 (2003-04-01), Kuo
patent: 6911691 (2005-06-01), Tomiie et al.
patent: 2004/0232470 (2004-11-01), Zheng et al.
patent: 2005/0219900 (2005-10-01), Kamagaki et al.
A Novel 2-Bit/Cell MONOS Memory Device with a Wrapped-Control-Gate Structure that Applies Source-Side Hot-Electron Injection, Hideto Tomiya et al., 2002 IEEE Symposium on VLSI Technology Digest of Technical Papers.
90-nm-node Multi-Level AG-AND Type Flash Memory with Cell Size of True 2 F2/bit and Programming throughput of 10MB/S, Y. Sasago et al., 2003 IEEE.

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