Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-12-20
2005-12-20
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S660000, C438S663000
Reexamination Certificate
active
06977219
ABSTRACT:
The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure and developed resist pattern is exposed to a solvent prior to a bake or reflow process. Exposure to the solvent lowers the molecular weight of the resist material, modifying the resist material's reflow rate. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole or line size of the patterned resist.
REFERENCES:
patent: 6210868 (2001-04-01), Yoshii
patent: 6485895 (2002-11-01), Choi et al.
Frost Rex K.
Sivakumar Swaminathan
Blakely , Sokoloff, Taylor & Zafman LLP
Dang Phuc T.
Intel Corporation
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