Solid phase epitaxy activation process for source/drain...

Details Solid phase epitaxy activation process for source/drain... Solid phase epitaxy activation process for source/drain...

2000-08-07

2003-02-18

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S528000

Reexamination Certificate

active

06521502

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits (ICs) and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a low thermal budget method of manufacturing an integrated circuit utilizing solid phase epitaxy.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) or MOSFETs. The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Thus, controlling short channel effects is important to assuring proper semiconductor operation.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacers.
As transistors disposed on ICs become smaller, CMOS fabrication processes have utilized channel doping techniques. One technique utilizes shallow pocket regions which effectively suppress the short-channel effect (which degrades the robustness of the transistor to random process variations). Shallow pocket regions are provided in a conventional CMOS pocket implant process. The implant process is performed after the gate structure is fabricated and before the silicide layers are formed. The shallow pocket regions are not deeper than the source and the drain regions.
Another channel doping technique utilizes a two-dimensional doping implant, which is achieved by forming deep pocket implant regions, wherein the channel-doping profile in the lateral direction is non-uniform and the channel-doping profile in the vertical direction is a super-steep retrograded channel-doping profile. The two-dimensional channel-doping profile is critical to scaling (i.e., proportional operation) and structural elements in the ultra-small dimensions of the MOSFET). The deep pocket implant regions are conventionally formed after the extensions, drain and source regions and spacers are formed. The deep pocket results in a “halo-like” structure (e.g., halo regions). It is desirous to maintain the halo regions in a localized portion of the substrate.
As the critical dimensions of transistors continue to be reduced (e.g., to achieve a gate length of 50 nm and below), control of thermal budget in IC fabrication is very important. The term ‘thermal budget’ refers to the temperature applied to the substrate during the fabrication process. The formation of ultra-shallow source/drain extensions and a super-localized halo profile for the halo regions is critical to control short-channel effects. In conventional CMOS processes, high temperature (e.g., greater than 1000° C.) rapid thermal annealing (RTA) is used to activate the dopant in the source region, drain region, halo region, etc. However, the high temperature RTA can adversely affect the formation of the source, drain and halo regions.
With continually-shrinking MOSFET dimensions, high-k materials (i.e., materials having a high dielectric constant or k, such as, Al
2
O
3
, TiO
2
, ZrO
2
, etc.) can also be used as gate insulators. Unfortunately, high-k materials tend to react with silicon at high temperatures. As such, the processing temperature has to be kept low (e.g., <800° C.) if high-k materials are to be used as gate dielectrics. Accordingly, conventional CMOS processes cannot readily employ high-k gate dielectrics due to the adverse affects of the high temperature RTA.
Thus, there is a need for a manufacturing process for CMOS integrated circuits in which post-gate processing temperatures are lower such that high-k materials used as gate insulators do not react with silicon. Further, there is a need for a transistor fabrication process which uses a differential anneal strategy. Even further, there is a need for using an amorphous implant before the halo region, the shallow source/drain extensions and deep source/drain contact junctions are formed. Even further still, there is a need for an IC manufacturing process in which highly activated source/drain extensions, deep source/drain contact junctions and halo regions are created.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing a transistor. The method includes providing a gate structure, providing a deep amorphous implant, providing a shallow dopant implant, providing a tilted angle halo implant, and forming a pair of spacers abutting the gate structure. The method also includes providing a deep source/drain dopant implant and annealing at a low temperature. The annealing at the low temperature activates dopants from the shallow extension dopant implant, the halo dopant implant, and the deep source/drain dopant implant via solid phase epitaxy.
Another exemplary embodiment relates to a process of forming a transistor on a substrate. The substrate includes a gate conductor. The process includes forming a deep amorphous region, doping a shallow portion of the deep amorphous region, doping a halo region at least partially in the deep amorphous region, and doping a deep portion of the deep amorphous region for deep source and drain regions. The method also includes recrystallizing the deep amorphous region.
Yet another embodiment relates to a method of manufacturing a transistor on an ultra-large scale integrated circuit. The method includes steps of amorphizing a deep amorphous region in a substrate, implanting a dopant into a shallow portion of the deep amorphous region of the substrate to form a source extension and a drain extension, implanting a dopant into a deep portion of the deep amorphous region to form a deep source and drain region, and recrystallizing the deep amorphous region.


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