Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
1998-04-20
2001-04-24
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S780000, C257S781000
Reexamination Certificate
active
06222279
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic device manufacturing methods and structures, and more particularly to methods of forming electrical and mechanical connections for a microelectronic device, and the connections so formed.
BACKGROUND OF THE INVENTION
High performance microelectronic devices often use solder balls or solder bumps for electrical interconnection to other microelectronic devices. For example, a very large scale integration (VLSI) chip may be electrically connected to a circuit board or other next level packaging substrate using solder balls or solder bumps. This connection technology is also referred to as “Controlled Collapse Chip Connection—C4” or “flip-chip” technology, and will be referred to herein as solder bumps.
In the original solder bump technology developed by IBM, the solder bumps are formed by evaporation through openings in a shadow mask which is clamped to an integrated circuit wafer. For example, U.S. Pat. No. 5,234,149 entitled “Debondable Metallic Bonding Method” to Katz et al. discloses an electronic device with chip wiring terminals and metallization layers. The wiring terminals are typically essentially aluminum, and the metallization layers may include a titanium or chromium localized adhesive layer, a co-deposited localized chromium copper layer, a localized wettable copper layer, and a localized gold or tin capping layer. An evaporated localized lead-tin solder layer is located on the capping layer.
Solder bump technology based on an electroplating method has also been actively pursued. The electroplating method is particularly useful for larger substrates and smaller bumps. In this method, an “under bump metallurgy” (UBM) layer is deposited on a microelectronic substrate having contact pads thereon, typically by evaporation or sputtering. A continuous under bump metallurgy layer is typically provided on the pads and on the substrate between the pads, in order to allow current flow during solder plating.
An example of an electroplating method with an under bump metallurgy layer is disclosed in U.S. Pat. No. 5,162,257 entitled “Solder Bump Fabrication Method” to Yung and assigned to the assignee of the present application. In this patent, the under bump metallurgy layer contains a chromium layer adjacent the substrate and pads, a top copper layer which acts as a solderable metal, and a phased chromium/copper layer between the chromium and copper layers. The base of the solder bump is preserved by converting the under bump metallurgy layer between the solder bump and contact pad into an intermetallic of the solder and the solderable component of the under bump metallurgy layer. Multiple etch cycles may, however, be needed to remove the phased chromium/copper layer and the bottom chromium layer. Even with multiple etch cycles, the under bump metallurgy layer may be difficult to remove completely, creating the risk of electrical shorts between solder bumps.
Notwithstanding the above mentioned patents, there still exists a need in the art for methods for forming solder bumps and solder bump structures formed thereby wherein the exposed portion of the under bump metallurgy layer can be readily and completely removed after electroplating the solder bumps thereby reducing the possibility of electrical shorts between solder bumps. There also exists a need in the art for a method for forming solder bumps wherein the solder bump need not be significantly undercut when the exposed portion of the under bump metallurgy layer is removed thereby reducing the possibility of mechanical or electrical failure.
SUMMARY OF THE INVENTION
It is therefor an object of the present invention to provide an improved method for fabricating solder bumps for microelectronic device contact pads, and improved solder bumps formed thereby.
It is another object of the present invention to reduce the time required to remove the exposed portion of the under bump metallurgy layer after electroplating the solder bump.
It is still another object of the present invention to reduce electrical shorts between solder bumps.
It is yet another object of the present invention to reduce the undercutting of solder bumps when the under bump metallurgy layer is removed after electroplating.
These and other objects are provided according to the present invention by depositing a continuous titanium barrier layer on the microelectronic device before forming the under bump metallurgy layer. Accordingly, the under bump metallurgy layer can be selectively removed from the titanium layer, and the titanium layer can then be removed from the microelectronic device. The titanium layer prevents the under bump metallurgy layer from forming residues on the microelectronic device which could result in electrical shorts between solder bumps. In addition, the titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer.
According to one aspect of the present invention, a method for forming solder bumps includes the steps of depositing a titanium barrier layer on the microelectronic device including contact pads, forming an under bump metallurgy layer on and in contact the titanium barrier layer, and then forming a solder bump on the under bump metallurgy layer whereby the solder bump is spatially separated from the titanium barrier layer. The solder bump defines exposed portions of the under bump metallurgy layer and the titanium barrier layer which are each selectively removed. Accordingly, the exposed portions of the under bump metallurgy layer can be quickly and completely removed after electroplating solder bumps without significantly undercutting the solder bumps or leaving residues which could result in shorts between solder bumps.
The exposed portion of the under bump metallurgy layer can be selectively removed using etchants which attack the under bump metallurgy layer preferentially with respect to the solder bump and the titanium barrier layer. The titanium barrier layer can then be selectively removed using an etchant that preferentially attacks the titanium barrier layer with respect to the solder bump and the portion of the under bump metallurgy layer remaining beneath the solder bump.
The under bump metallurgy layer preferably comprises a chromium layer on the titanium barrier layer, a phased layer of chromium and copper on the chromium layer, and a copper layer on the phased layer. In this embodiment, a mixture of ammonium hydroxide and hydrogen peroxide can be used to selectively etch the copper portions of the under bump metallurgy layer; hydrochloric acid can be used to etch the chromium portions of the under bump metallurgy layer; and hydrofluoric acid buffered with ammonium fluoride can be used to selectively etch the titanium layer.
A solder dam can also be formed on the under bump metallurgy layer in areas not to be covered by the solder bump, and this solder dam is preferably removed before removing the exposed portions of the under bump metallurgy layer. The solder dam preferably includes a solder non-wettable layer such as a chromium or titanium layer. The solder dam may also include a layer of a solder wettable material, such as copper, on the solder non-wettable layer.
After formation, the solder bump can be reflowed. The step of reflowing the solder bump can generate a reaction between the solder bump and the unexposed portion of the under bump metallurgy layer adjacent the solder bump resulting in an intermetallic region wherein the etchant used to remove the copper portions of the under bump metallurgy layer attacks copper preferentially with respect to the intermetallic region.
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patent: 4950623 (19
Adema Gretchen Maerker
Kellam Mark D.
Mis Joseph Daniel
Rogers W. Boyd
Alston & Bird LLP
Clark Sheila V.
MCNC
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