SOI transistor with self-aligned ground plane and gate and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S680000, C438S786000, C438S787000, C257SE21170, C257SE21051, C257SE21058, C257SE21320, C257SE21259, C257SE21267, C257SE21278, C257SE21330, C257SE21332, C257SE21370

Reexamination Certificate

active

07910419

ABSTRACT:
A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.

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French Preliminary Search Report, FR 08 53868, dated Feb. 13, 2009.

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