SOI stacked DRAM logic

Details SOI stacked DRAM logic SOI stacked DRAM logic

2000-03-17

2003-04-08

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S455000

Reexamination Certificate

active

06544837

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits and, more particularly, to high capacity dynamic random access memories including high performance transistors in support circuitry thereof and other types of devices having differing circuit element requirements and to testing and burn-in thereof.
2. Description of the Prior Art
As the processing power of microprocessors has increased and cycle times reduced, higher capacity memories with more rapid access time have been demanded. Accordingly, dynamic memories have been developed with storage cells requiring reduced area or footprint such that memory chips having a capacity of a gigabit or more can be foreseen. Such storage cells are often formed by lining trenches in a chip of doped semiconductor with an insulator and filling the remainder of the trench with doped polysilicon to form an array of capacitors having a common electrode formed by the chip. A storage cell of such an array is generally referred to as a trench capacitor.
Substantial circuitry for accessing particular storage cells and sensing the charge stored therein is also required such as decoders, bit line drivers and sense amplifiers collectively referred to as “support circuits”. It is desirable and, at the present state of the art, substantially necessary to form support circuits on the same chip as the memory array. However, the support circuitry requires substantial chip area which is thus not available for formation of memory cells. Also, larger arrays imply longer word and bit lines which are necessarily of increased capacitance while storage cell size reduction tends to, decrease capacitance of each storage cell. A reduction of the ratio of these capacitances reduces the voltage available to sense amplifiers and increases the criticality of sense amplifier operating margins.
Higher switching speeds and reduced cycle times have required new transistor technologies as well as high integration densities to reduce signal propagation time. At the present time, high performance transistors are often formed using silicon-on-insulator (SOI) technology because of the well-known device advantages of SOI such as reduced junction capacitance, latch-up immunity, improved isolation, steeper sub-Vt slope, reduced back-bias sensitivity and the like. Transistors fabricated using SOI technology provide particularly low power dissipation and high speed operation at low voltages (e.g. less than 1.5 volts).
A SOI wafer will typically comprise a relatively thin layer of silicon formed on an insulator which is, in turn supported by a bulk silicon wafer in order to withstand processing to form the active devices. The bulk silicon wafer has no electrical function and is fully insulated from any active devices which may be formed. SOI wafers may be formed in different ways including lamination of oxide-covered substrates oxide-to-oxide by heat treatment.
A leading process for constructing an SOI wafer is disclosed in “‘Smart Cut’; A Promising New SOI Material Technology” by M. Bruel et al.; Proceedings 1995 IEEE International SOI Conference; October, 1995, which is hereby fully incorporated by reference. This process includes the steps of implanting hydrogen into a first silicon wafer capped with oxide, room temperature hydrophilic bonding to a second wafer of bare silicon or oxide capped silicon, heat treatment of the bonded wafers at 400° C.-600° C. to cleave the wafers at a location within the silicon of the first wafer leaving the oxide cap(s) embedded and covered by a very thin layer of monocrystalline silicon from the first wafer bonded to and supported by the second wafer. The wafer is completed by a final chemical-mechanical polish step to reduce the surface roughness to a small fraction of a nanometer.
However, SOI transistors and trench capacitors are not compatible and cannot be easily integrated on the same chip. For example, voltages required for testing and burn-in of trench capacitors is greater than the breakdown voltage of the thin gate oxide of high performance field effect transistors. Further, the active device layer of SOI wafers is too thin to provide adequate capacitance at currently feasible minimum lithographic feature sizes and forming a trench through the insulator of an SOI wafer or chip would compromise the electrical isolation thereof. Moreover, the thermal budget required to form trench capacitors and node interconnections greatly exceeds the desired heat budget for forming high speed, low voltage logic switching devices in SOI.
Another problem involving on-chip capacitances required in increasing numbers of types of integrated circuits is the decoupling capacitance which is required in logic circuits operating at low voltage and clock frequencies greater than about 400 MHz to prevent unacceptable levels of switching noise (relative to the operating voltage) from being propagated through power connections. The intrachip area required for a planar capacitor is so large that multiple power supplies to reduce power/performance trade-offs cannot be included on the chip since the voltage regulators cannot be adequately decoupled with the capacitors which can be provided.
Incompatible technologies have been functionally reconciled to a degree by separately forming respective circuits on semiconductor substrates by different processes and bonding the respective substrates together to form a unitary chip. Many different structures have been used for this purpose including the stacking of chips. However, when chips are stacked, interchip connections other than at edges of the chips cannot be reliably formed at minimum lithography feature size and the available area of the edges limits the number of connections which can be made. By the same token, interchip connection pitches cannot approach the fineness of intrachip connection pitches. For both of these reasons, the number of interchip connections that can be reliably formed and used is very limited and is certainly insufficient for memory capacities which can be foreseen. Connections at the edges of chips are also not optimally short to limit signal propagation time.
Accordingly, there has been no solution to providing transistors of improved performance on the same chip with trench capacitor arrays while the need for faster access time and larger numbers of storage cells and high speed logic for accessing them has not been fully answered using technologies which are compatible with each other or incompatible technologies on separately processed, commonly packaged chips. Therefore, the current state of the art does not support significant further increases in either memory capacity or performance and requires substantial processing to both align the chip faces and seal the interchip wiring from external atmosphere which could cause deterioration thereof.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a single chip having both a large array of trench capacitors and high performance SOI field effect transistors in support circuits.
It is another object of the invention to provide structures allowing large trench decoupling capacitors in combination with an SOI chip.
It is yet another object of the invention to provide a layered semiconductor chip utilizing different device technologies in respective layers.
It is a further object of the invention to provide a layered semiconductor chip where the length of connections between devices in respective layers can be minimized and provided over any or all regions of the chip.
It is yet another object of the invention to provide a novel technique of laminating semiconductor chips where circuit elements have been formed on at least one of the chips at the time of lamination.
It is another further object of the invention to provide a technique of forming a semiconductor integrated circuit device in which arbitrary circuit elements can be formed consistent with a restricted heat budget for gate oxides of high performance field effect transistors.
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