SOI MOSFETS exhibiting reduced floating-body effects

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S151000, C438S305000, C438S306000, C438S525000, C438S530000

Reexamination Certificate

active

10732277

ABSTRACT:
Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

REFERENCES:
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 4984043 (1991-01-01), Vinal
patent: 5151759 (1992-09-01), Vinal
patent: 5185280 (1993-02-01), Houston et al.
patent: 5225357 (1993-07-01), Ho
patent: 5244823 (1993-09-01), Adan
patent: 5364807 (1994-11-01), Hwang
patent: 5409848 (1995-04-01), Han et al.
patent: 5422506 (1995-06-01), Zamapian
patent: 5536962 (1996-07-01), Pfiester
patent: 5585285 (1996-12-01), Tang
patent: 5650340 (1997-07-01), Burr et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 5767557 (1998-06-01), Kizilyalli
patent: 5793090 (1998-08-01), Gardner et al.
patent: 5821147 (1998-10-01), Kizilyalli
patent: 5923987 (1999-07-01), Burr
patent: 5930642 (1999-07-01), Moore et al.
patent: 5936278 (1999-08-01), Hu et al.
patent: 6127222 (2000-10-01), Luning et al.
patent: 6204138 (2001-03-01), Krishnan et al.
patent: 6268640 (2001-07-01), Park et al.
patent: 6271095 (2001-08-01), Yu
patent: 6306712 (2001-10-01), Rodder et al.
patent: 6353245 (2002-03-01), Unnikrishnan
patent: 6368928 (2002-04-01), Wang et al.
patent: 6472282 (2002-10-01), Yu
Wolf, Ph.D., Stanley, “MOS Devices and NMOS Process Integration,” Silicon Processing for the VLSI Era—vol. 2: Process Integration, Lattice Press, 1990, pp. 298-301.
Wolf, Ph.D., Stanley, “Isolation Technologies for Integrated Circuits,” Silicon Processing for the VLSI Era—vol. 2: Process Integration, Lattice Press, 1990, pp. 72-75.
Kamgar et al., Ultra-High Speed CMOS Circuits in Thin SIMOX Films, IEDM, 1989, 829-832.
Shahidi et al., Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing, IEDM, 1990, 587-590.

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