SOI MOSFET with graded source/drain silicide

Details SOI MOSFET with graded source/drain silicide SOI MOSFET with graded source/drain silicide

2001-07-05

2002-10-15

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S295000, C438S303000, C438S683000, C257S347000, C257S382000, C257S384000

Reexamination Certificate

active

06465313

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to semiconductor-on-insulator devices and methods for forming the same. The invention relates particularly to semiconductor-on-insulator devices and methods for forming which avoid or reduce floating body effects.
BACKGROUND ART
Semiconductor on insulator (SOI) materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are “floating”). However, partially-depleted metal oxide semiconductor field effect transistors (MOSFETs) on SOI materials typically exhibit parasitic effects due to the presence of the floating body (“floating body effects”). These floating body effects may result in undesirable performance in SOI devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a semiconductor device. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween; the semiconductor layer including a source region, a drain region, and a body region disposed between the source and drain regions, the source and drain regions including respective source and extensions which extend partially laterally inwardly towards one another above the body region; and, a gate on the semiconductor layer disposed above the body region, the gate being operatively arranged with the source, drain, and body regions to form a transistor; wherein the source and drain regions include source and drain deep doped regions on opposite sides of and laterally spaced from the gate and laterally adjacent to the respective source and drain extensions, and wherein the source and drain extensions include respective source and drain silicide extension portions disposed therein of a first thickness and the source and drain deep doped regions include respective source and drain silicide deep portions disposed therein of a second thickness relatively thicker than the first thickness.
According to another aspect of the invention, the invention is a method of forming a semiconductor device. The method includes the steps of forming an SOI wafer having a semiconductor layer, a substrate and a buried insulator layer therebetween, wherein the semiconductor layer includes a source region, a drain region, and a body region disposed between the source and drain regions, the source and drain regions including respective source and drain extensions which extend partially laterally inwardly towards one another above the body region; forming a gate on the semiconductor layer above the body region; forming source and drain deep doped regions on opposite sides of and laterally spaced from the gate and laterally adjacent to the respective source and drain extensions; and, forming source and drain silicide extension portions of a first thickness in the respective source and drain extensions and source and drain silicide deep portions of a second thickness relatively thicker than the first thickness in the respective source and drain deep doped regions.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 6051473 (2000-04-01), Ishida et al.
patent: 6121100 (2000-09-01), Andideh et al.
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6340829 (2002-01-01), Hirano et al.
patent: 6346732 (2002-02-01), Mizushima et al.

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