Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-11-01
1999-08-17
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711206, G11C 1210
Patent
active
059408723
ABSTRACT:
A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage location in the TLB for storing at least a portion of a second virtual to physical memory translation. The second storage location in the TLB is only software-managed.
REFERENCES:
patent: 4774653 (1988-09-01), James
Bryg William R.
Burger Stephen G.
Hammond Gary N.
Hays James O.
Ross Jonathan K.
Intel Corporation
Lane Jack A.
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