Soft error immunity in CMOS circuits with large shared diffusion

Details Soft error immunity in CMOS circuits with large shared diffusion Soft error immunity in CMOS circuits with large shared diffusion

1998-09-23

2000-07-11

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 34, 326 31, 326 26, 326 27, 326119, 326112, 326121, 257921, 257659, H03K 1923, H03K 19094, H01L 29167, H01L 23552

Patent

active

060878495

ABSTRACT:
A CMOS logic circuit comprises a logic gate having an input node (e.g., a storage node) coupled to a positive supply potential through a p-type field-effect transistor (PFET), with one or more n-type field-effect transistors (NFETs) being coupled between the storage node and a negative supply potential. Since the response of the circuit to a high-energy particle strike is dominated by the N+ diffusion associated with the NFETs when the state of the storage node is high, i.e., a logical "1", the gate has a switching point that is set closer to the negative supply potential than to the positive supply potential.

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