Snooper circuit of a multi-processor system

Details Snooper circuit of a multi-processor system Snooper circuit of a multi-processor system

1997-04-18

1998-10-27

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1300

Patent

active

058290400

ABSTRACT:
A snooper circuit of a multi-processor system includes a plurality of processor boards each having a central processing unit, a cache memory, a cache controller to control the cache memory and a snooper controller, a main memory, and a system bus for interconnecting these. The snooper circuit comprises an address tag memory, a state tag memory, a first comparator, a second comparator and the snooper controller for judging the address match between the other requester and the snooper controller by receiving the output of the first comparator, judging whether bus operation for the same address is doubly requested before the bus operation is finished by receiving the output of the second comparator, offering output predetermined cache coherency signal on the system bus according to the judged result and the address match signal between the other requester and the cache memory, and offering output first control signal for write-back, second control signal for updating state, third control signal for controlling a data buffer and fourth control signal for retrying of the CPU and referring or updating the data of the state tag memory, and maintains the cache coherency between the main memory and the cache memories.

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