Small-sized static random access memory cell

Details Small-sized static random access memory cell Small-sized static random access memory cell

1997-08-05

1998-12-22

Mai, Son

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, G11C 1134

Patent

active

058525726

ABSTRACT:
A SRAM cell includes a single line used as both a word line and a power supply voltage line, a first and a second load element, a first and a second NMOS driver transistor, and a first and a second PMOS access transistor. Each of the two load elements is connected between the line and one of two storage nodes. The first load element is connected between the single line and a first storage node. The second load element is connected between the single line and a second storage node. The first NMOS driver transistor is connected between the first storage node and ground. The second driver transistor is connected between the second storage node and ground. The first access transistor is connected between the first storage node and a bit line and the second access transistor is connected between the second storage node and a complementary bit line. The first and second access transistors have gates commonly connected to the single line. The layout of the SRAM cell is simplified and the cell layout area is reduced because a single line is used as both the power supply voltage line and the word line.

REFERENCES:
patent: 4653025 (1987-03-01), Minato et al.
patent: 5521861 (1996-05-01), Lee et al.
patent: 5570312 (1996-10-01), Fu
patent: 5600589 (1997-02-01), Ishigaki

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