Small area, robust silicon via structure and process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S637000, C257S621000, C257SE21585

Reexamination Certificate

active

07902069

ABSTRACT:
A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

REFERENCES:
patent: 6268660 (2001-07-01), Dhong et al.
patent: 2002/0142592 (2002-10-01), Barth et al.
patent: 2004/0108367 (2004-06-01), Farooq et al.
patent: 2005/0101054 (2005-05-01), Mastromatteo
patent: 2005/0121768 (2005-06-01), Edelstein et al.
patent: 2006/0001174 (2006-01-01), Matsui
patent: 2007/0048896 (2007-03-01), Andry et al.
patent: WO2007024022 (2007-03-01), None

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