Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-07-30
2004-09-07
Nguyen, Vìet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S225700, C365S200000, C365S191000
Reexamination Certificate
active
06788587
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to blowing of anti-fuses in an integrated circuit, and more particularly, to a small anti-fuse circuit to facilitate parallel anti-fuse blowing.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers are under increasing pressure to improve the capacity and performance of semiconductor devices. For example, memory devices having an increasing number of individual memory elements are in demand, as well as devices that function at increased operating rates.
One consequence of this pressure is that all semiconductor operations are under increased scrutiny to determine where performance improvements may be gained. Among the semiconductor operations scrutinized is the time required to program anti-fuse devices used to configure redundant circuit elements.
For example, it may be necessary to replace defective or otherwise undesired circuit elements in an integrated circuit. Modern integrated circuits are designed having multiple redundant circuit elements available to provide replacement circuit elements, the replacement circuit elements being separated from the active circuit by anti-fuse devices. One method of replacing circuit elements includes reconfiguring the circuit by blowing the separating anti-fuse devices. By blowing an anti-fuse device, a first circuit element may be activated to replace a second circuit element that may likewise be deactivated.
One example of redundant circuit elements is the common use in a memory device of redundant rows and/or columns of memory cells to replace one or more rows and/or columns of primary memory which contain defective cells.
Because each integrated circuit includes many circuit elements, and hence includes many redundant circuit elements, programming the anti-fuse devices can be a complex and time-consuming process. For instance, anti-fuse devices and the accompanying redundant circuit elements are typically configured such that the anti-fuse devices must be programmed individually in series. For integrated circuits having many anti-fuse devices to be programmed, the serial programming of anti-fuse devices may consume valuable time and resources. As integrated circuit devices increase in size, the time required to program the anti-fuse devices likewise increases significantly.
Accordingly, there is a strong desire and need to improve the performance of integrated circuits by providing a method of programming a plurality of anti-fuse devices substantially simultaneously.
BRIEF SUMMARY OF THE INVENTION
An apparatus and associated method are provided to facilitate the programming of anti-fuse devices in an integrated circuit. An anti-fuse programming circuit is described that is capable of programming a plurality of anti-fuse devices in parallel. This circuit permits multiple anti-fuses to be blown substantially simultaneously using one common programming signal.
The programming circuit of the invention includes a plurality of programmable elements and a plurality of programming circuits, each associated with a programmable element and each including a latch circuit for receiving and holding a desired programming state of an associated programmable element. The plurality of programming circuits set the states of the associated programmable elements in accordance with a desired programming state held in an associated latch circuit in response to a common control signal.
In another aspect of the invention, the programming circuit includes a latch circuit; a latch-programming circuit configured to temporarily apply a programming signal to an input of the latch circuit, the latch circuit latching a state of the programming signal; a signal line applying a voltage sufficient to change the state of the programmable element; a latch isolation transistor coupled between the programmable element and the latch circuit; a state control transistor coupled between the programmable element and a first reference voltage and having a gate controlled by an output of the latch circuit; wherein during a programming phase, the anti-fuse latch circuit is configured to latch the soft-programming signal, and during a common control phase, the latch isolation transistor is configured to decouple the programmable element from the latch circuit and the signal line is configured to apply the state-changing voltage to the programmable element if the output of the latch circuit turns on the state control transistor.
In another aspect of the invention, the invention provides a method of programming a plurality of programmable elements, including soft-programming a plurality of latches to a desired state, each latch associated with a respective programmable element, and hard-programming the plurality of programmable elements with the state of an associated latch using a common control signal.
In another aspect of the invention, the method of programming the anti-fuse includes providing a state control transistor coupled between the programmable element and a first reference voltage; providing a latch circuit having an input coupled to the programmable element through a latch isolation transistor and an output coupled to control a gate of the state control transistor; during a programming phase, applying a programming signal to the input of the latch circuit, and latching the programming signal in the latch circuit; during a common control phase, applying a voltage sufficient to change a state of the programmable element if an output of the latch circuit activates the state control transistor, and decoupling the programmable element from the latch circuit using the latch isolation transistor.
REFERENCES:
patent: 5294846 (1994-03-01), Paivinen
patent: 5838624 (1998-11-01), Pilling et al.
patent: 5838625 (1998-11-01), Cutter et al.
patent: 6016264 (2000-01-01), Lin
patent: 6128241 (2000-10-01), Choi
patent: 6185705 (2001-02-01), Cutter et al.
patent: 6240033 (2001-05-01), Yang et al.
patent: 6373771 (2002-04-01), Fifield et al.
patent: 6477094 (2002-11-01), Kim et al.
patent: 6628561 (2003-09-01), Van De Graaff
patent: 6630724 (2003-10-01), Marr
patent: 6633183 (2003-10-01), Duesman
patent: 6633506 (2003-10-01), Casper et al.
patent: 2001/0022746 (2001-09-01), Kim et al.
patent: 2002/0060941 (2002-05-01), Casper et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Vet Q.
LandOfFree
Small anti-fuse circuit to facilitate parallel fuse blowing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Small anti-fuse circuit to facilitate parallel fuse blowing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Small anti-fuse circuit to facilitate parallel fuse blowing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3220292