SLM display data address mapping for four bank frame buffer

Details SLM display data address mapping for four bank frame buffer SLM display data address mapping for four bank frame buffer

2002-12-04

2004-05-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230030, C365S230080

Reexamination Certificate

active

06741503

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to display systems that use spatial light modulators (SLMs), and more particularly to memory devices for storing and delivering data to the spatial light modulator.
BACKGROUND OF THE INVENTION
A Digital Micromirror Device™ (DMD™) is a type of spatial light modulator (SLM). SLMs are characterized by their ability to display entire frames of data simultaneously, as compared to scanning devices such as cathode ray tubes. An LCD (liquid crystal display) is another familiar type of SLM.
Invented in the 1980's at Texas Instruments Incorporated, the DMD operates as a microelectromechanical system (MEMS) device, having an array of tiny individually addressable reflective mirrors. The DMD can be combined with image processing, memory, a light source, and optics to form a digital light processing system capable of projecting large, bright, high-contrast color images.
The DMD is fabricated using CMOS-like processes over a CMOS memory. Each mirror can reflect light in one of two directions depending on the state of an underlying memory cell. With the memory cell in a first state, the mirror rotates to +10 degrees. With the memory cell in a second state, the mirror rotates to −10 degrees. When the mirror surfaces are illuminated with a light source, the mirrors in the array can be set to one state or the other, such that “on” mirrors reflect light to one location and “off” mirrors reflect light to another location. For imaging applications, the “on” mirror elements reflect light to an image plane. The “on” state of the mirror appears bright and the “off” state of the mirror appears dark.
Grayscale is achieved by binary pulse width modulation (PWM) of the incident light. Color is achieved by using color filters, either stationary or rotating, in combination with one, two, or three DMD chips.
For simplicity, the PWM technique may be illustrated for a 4-bit word (2
4
or 16 gray levels). Each bit in the word represents a time duration for light to be on or off (1 or 0). The time durations have relative values of 2
0
, 2
1
, 2
2
, 2
3
, or 1, 2, 4, 8. The bit with the shortest interval (Bit
0
) is called the least significant bit (LSB). The bit with the longest interval (Bit
3
) is called the most significant bit (MSB). The period for displaying each frame of data is divided into four time durations of 1/15, 2/15, 4/15, and 8/15 of the frame period. The possible gray levels produced by all combinations of bits in the 4-bit word are 2
4
or 16 equally spaced gray levels (0, 1/15, 2/15 . . . 15/15). Thus, for each frame of display data, the binary values of the “bit weights” that comprise each pixel's data determine the duration of time that the pixel will be “on” within that frame.
Visual artifacts can be reduced by a “bit-splitting” technique. In this technique, the longer duration bits are subdivided into shorter durations, and these split bits are distributed throughout the video field time. DLP displays combine pulsewidth modulation and bit-splitting to produce a “true-analog” sensation.
A frame memory is used to supply data to the DMD. The frame memory is comprised of DRAM memory devices, which typically operate in a “double buffer” mode. That is, one buffer is accessed for writing data into the frame memory, and a second buffer is accessed for reading data out of the frame memory to the DMD. Because of the manner in which the DMD displays data, the data must be available to the DMD according to pixel position and by the bit weight within each pixel “word”.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.
An advantage of the invention is that it permits interleaving of three different frame memory operations: bit-plane writes, pixel position reads, and read/write toggling. This is accomplished in a four bank memory by using the two bank address bits for write and read interleaving, and placing the read/write address bit in the MSB of the column address. This has the added benefit of eliminating refresh requirements for low frame rates. The result is fewer overhead cycles, which makes faster load times possible, as well as reduced manufacturing time and cost.


REFERENCES:
patent: 6480433 (2002-11-01), Huffman
patent: 2002/0085438 (2002-07-01), Wolverton

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