Sliding grid based technique for optimal on-chip decap...

Details Sliding grid based technique for optimal on-chip decap... Sliding grid based technique for optimal on-chip decap...

2002-05-10

2003-09-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06625791

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) all that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (
10
).
The various computations and operations performed by the computer system are facilitated through the use of signals that provide electrical pathways for data to propagate between the various components of the computer system. In a general sense, the passing of data onto a signal may occur by either raising the voltage of the signal or reducing the voltage of the signal. When the voltage is raised, the signal is said to be at a “logic high,” and when the voltage is reduced, the signal is said to be at a “logic low.” Typically, changes in the voltage value of a signal are controlled by a signal driver, e.g., a logic gate, attached to the signal wire on which the signal resides. Switching the logical output of the signal driver from low-to-high or from high-to-low charges or discharges decoupling capacitors associated with the signal wire, which, in turn, raises or lowers the voltage value of the signal.
Usually, decoupling capacitors, referred to herein as “decap cells,” are designed as rectangular basic cells that may be arrayed into on-chip white-spaces, i.e., chip regions devoid of logic circuits. White-spaces on an integrated circuit may be located in various regions of the integrated circuit and may be of arbitrary rectilinear shape. Further, white-spaces may be either implicitly present or explicitly created in the design of the integrated circuit.
With the increasing frequency and current requirements of integrated circuits, more on-chip decoupling capacitance, referred to herein as “decap,” is required to provide the instantaneous charge requirements of the switching logic gates. As a result, increasing amounts of chip area are required for implementing decap. Thus, it is increasingly important that decap cells be arrayed into a white-space in a floorplan layout that allows as many decap cells as possible to be inserted.
SUMMARY OF INVENTION
According to one aspect of the invention, a method for arraying decoupling capacitors into a white-space of an integrated circuit comprises constructing a bounding box to encompass a periphery of the white-space; overlaying a grid onto a region of the integrated circuit demarcated by the bounding box; calculating a maximum number of decoupling capacitors that can be inserted into the white-space; and arraying the maximum number of decoupling capacitors into the white-space.
According to another aspect, a computer system comprises a processor; a memory; and instructions residing in the memory executable in the processor for constructing a bounding box to encompass a periphery of the white-space; overlaying a grid onto a region of the integrated circuit demarcated by the bounding box; calculating a maximum number of decoupling capacitors that can be inserted into the white-space; and arraying the maximum number of decoupling capacitors into the white-space.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 6385565 (2002-05-01), Anderson et al.
patent: 6487702 (2002-11-01), Lin et al.
patent: 6523159 (2003-02-01), Bernstein et al.
patent: 2001/0034587 (2001-10-01), Anderson et al.
patent: 2002/0144217 (2002-10-01), Lin et al.

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