Slew constrained minimum cost buffering

Details Slew constrained minimum cost buffering Slew constrained minimum cost buffering

2006-07-14

2008-11-04

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07448007

ABSTRACT:
A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.

REFERENCES:
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patent: 7191418 (2007-03-01), Lee et al.
L. Van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” IEEE Proceedings (ISCAS) pp. 865-868 (1990).
J. Lillis et al., “Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model,” IEEE Journal of Solid State Circuits, vol. 31, No. 3, pp. 437-447 (1996).
C. Alpert et al., “A Practical Methodology for Early Buffer and Wire Resource Allocation,” ACM/IEEE Proceedings (DAC) pp. 189-194 (2001).
C. Alpert et al., “Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control,” IEEE/CAN Proceedings (ICCAD) pp. 408-415 (2001).

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