Skewing-suppressive output buffer circuit

Details Skewing-suppressive output buffer circuit Skewing-suppressive output buffer circuit

1999-01-21

2000-06-06

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

713503, G06F 112

Patent

active

060732458

ABSTRACT:
In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.

REFERENCES:
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5664166 (1997-09-01), Isfeld
patent: 5822571 (1998-10-01), Goodrum et al.

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