Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-05-15
2004-03-30
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S712000, C438S725000
Reexamination Certificate
active
06713395
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to metal-insulator-metal (MIM) capacitors.
BACKGROUND OF THE INVENTION
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions and personal computing devices, as examples. Such integrated circuits typically use multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
One type of semiconductor device is a MIM capacitor, which comprises a bottom capacitive plate formed in a metallization layer, a top capacitive plate in an overlying layer, the top and bottom plates being separated by a capacitor dielectric layer. MIM capacitors are used frequently in mixed signal devices and logic devices, for example.
A problem with manufacturing MIM capacitors is that the capacitor dielectric separating the two capacitive plates is very thin, e.g., 500 to 700 Angstroms thick. This can result in very high leakage currents due to conductive particles, e.g. from etching the plates, that may be present at the site of the capacitor dielectric. As a result, MIM capacitor designs typically comprise a top metal plate that is smaller in area than the bottom metal plate to prevent high leakage currents and shorts.
Because most MIM capacitors have this step-like construction from the bottom to top plates, a separate lithography and etch step is required to form each of the top and bottom capacitor plates. This requires the use of two masks, two lithography steps, and two etch steps, one each for the bottom plate and the top plate.
What is needed in the art is a method of manufacturing MIM capacitors that has fewer etch steps, reduced complexity and a cost reduction compared to prior art MIM capacitor manufacturing methods.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented by the present invention, which achieves technical advantages as a method of simultaneously forming top and bottom plates of a MIM capacitor. A first resist is used to provide the pattern for the bottom metal plate, and a second resist is used to provide the pattern for the top metal plate of a MIM capacitor. The combined patterns of the first and second resist are simultaneously transferred to the underlying metallization layers in a single reactive ion etch (RIE) process.
Disclosed is a method of patterning metal layers of a semiconductor wafer, the method comprising depositing a first conductive layer over a substrate, depositing an insulating layer over the first conductive layer, depositing a second conductive layer over the insulating layer, depositing a first resist over the second conductive layer, depositing a second resist over the first resist, patterning the first resist with a first pattern, patterning the second resist with a second pattern, and simultaneously transferring the first pattern to the first conductive layer and the second pattern to the second conductive layer.
Also disclosed is a method of patterning metal layers of a semiconductor wafer, the wafer comprising a first conductive layer, an insulating layer disposed over the first conductive layer and a second conductive layer disposed over the insulating layer. The method comprises depositing a first resist over the second conductive layer, patterning the first resist with a first pattern, depositing a second resist over the first resist, patterning the second resist with a second pattern, and simultaneously transferring the first pattern to the first conductive layer and transferring the second pattern to the second conductive layer.
Further disclosed is a method of forming capacitive plates of a MIM capacitor, comprising providing a wafer having a substrate, depositing a first conductive layer on the substrate, depositing a capacitor dielectric layer over the first conductive layer, depositing a second conductive layer over the capacitor dielectric layer, depositing a first resist over the second conductive layer, patterning the first resist with a first pattern, depositing a second resist over the first resist, patterning the second resist with a second pattern, simultaneously transferring the first pattern to the first conductive layer and transferring the second pattern to the second conductive layer.
Advantages of the invention include providing a method of transferring the pattern of top and bottom metal plates simultaneously, resulting in less manufacturing process complexity. The invention results in fewer defects, reduced throughput and lower manufacturing costs. With the use of the single RIE pattern transfer method in accordance with the present invention, one RIE step, one resist strip, and one cleaning step may be eliminated in the manufacturing process for a MIM capacitor. The invention also results in improved yields because there is less chance of misalignment of the top and bottom capacitive plates.
REFERENCES:
patent: 4592132 (1986-06-01), Lee et al.
patent: 4657629 (1987-04-01), Bigelow
patent: 5492607 (1996-02-01), Yap
patent: 6284551 (2001-09-01), Cho et al.
patent: 6319767 (2001-11-01), Cha et al.
patent: 6420261 (2002-07-01), Kudo
Infineon - Technologies AG
Norton Nadine
Slater & Matsil L.L.P.
Umez-Eronini Lynette T.
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