Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-06-27
2003-04-01
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S455000
Reexamination Certificate
active
06541305
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of ball grid array interconnects and, more particularly, relates to ball grid array interconnects formed from single-melt solders having enhanced reliability.
In the electronics industry, it is known to mount an integrated circuit component to a ceramic or organic substrate by various means including wire bonds and so-called controlled collapse chip connections also known as C-4s. The wire bonds and C-4s not only provide the physical connection but also electrically connect electrical circuits on the integrated circuit component to appropriate electrical circuits on the ceramic or organic substrate. The mounting of the integrated circuit component on the ceramic or organic substrate is called first level packaging.
When using C-4s, it is useful to prevent the integrated circuit component from totally collapsing onto the ceramic or organic substrate. The reason for this is that the taller the joint height, the greater the fatigue resistance. One way to accomplish this is to have standoffs between the integrated circuit component and the ceramic or organic substrate. The prior art is replete with many solutions for providing such standoffs.
King et al. U.S. Pat. No. 3,871,014, the disclosure of which is incorporated by reference herein, discloses a flip-chip connection to a substrate in which the connection solder balls are non-uniform in shape. The result is that some of the solder balls act as standoffs to increase the joint height.
Lin et al. U.S. Pat. No. 3,871,015, the disclosure of which is incorporated by reference herein, discloses a flip-chip connection with non-uniform solder balls as was disclosed in King et al. above but, in addition, in
FIG. 5
discloses some of the standoffs to be copper balls.
Melton et al. U.S. Pat. No. 5,186,383, the disclosure of which is incorporated by reference herein, discloses the joining of an integrated circuit component to a substrate. The integrated circuit component has solder balls of a high melt composition. The substrate has pads of low melt solder. During joining of the integrated circuit component to the substrate, the assembly is heated to a temperature above the low melt solder but less than the high melt solder. The interaction of the low melt solder on the high melt solder causes the high melt solder to liquify at the junction of the low melt and high melt solder, thereby causing the solder balls to locally collapse. However, certain of the solder balls on the integrated circuit component do not have matching solder pads on the substrate so these solder balls do not liquify and collapse, thereby providing standoffs which control the collapse of the solder joint between the integrated circuit component and the substrate.
Nakanishi et al. U.S. Pat. No. 5,284,796, the disclosure of which is incorporated by reference herein, discloses a flip-chip joining process for connecting an integrated circuit component to a substrate. Connections between the integrated circuit component and the substrate are formed by mirror image solder bumps on the integrated circuit component and the substrate. Collapse of the joint is controlled by stud bumps at the edges of the integrated circuit component which are removed after the integrated circuit component has been joined to the substrate.
Pasch et al. U.S. Pat. No. 5,700,715, the disclosure of which is incorporated by reference herein, discloses a flip-chip connection to a substrate in which pillars are utilized to provide separation between the integrated circuit component and the substrate.
Gordon U.S. Pat. No. 5,895,554, the disclosure of which is incorporated by reference herein, discloses an alignment apparatus for use during the mounting of electronic components. Part of the function of the alignment apparatus is to control the collapse of the solder joint between the electronic components.
Ochiai Japanese Patent Application 3-30349, the disclosure of which is incorporated by reference herein, discloses the joining of a chip to a substrate. In one embodiment shown in
FIG. 1
, a chip and a substrate having mirror image solder bumps are joined together. Rubber spacers are utilized to keep the solder joint between the chip and substrate from collapsing. In a second embodiment shown in
FIG. 2
, solder bumps are initially formed only on the chip. Rubber spacers again keep the solder joint from collapsing.
Coombs IBM Technical Disclosure Bulletin, 16, No. 3, p.767 (August 1973), the disclosure of which is incorporated by reference herein, discloses solder pillars on a chip which are joined to solder deposits on a substrate. A shouldered pin controls the joint distance between the chip and substrate.
Aakalu IBM Technical Disclosure Bulletin, 22, No. 3, p.1064 (August 1979), the disclosure of which is incorporated by reference herein, discloses the use of solder spacers to control the spacing between a cap and a ceramic substrate.
Galloway et al. IBM Technical Disclosure Bulletin, 23, No. 5, pp.2156-2158 (October 1980), the disclosure of which is incorporated by reference herein, discloses a flip-chip arrangement for mounting a chip on a substrate wherein standoffs of a different alloy material than the solder used to join the chip to the substrate are utilized to maintain a controlled distance between the chip and the substrate.
Darrow et al. IBM Technical Disclosure Bulletin, 30, No. 11, pp. 320-321 (April 1988), the disclosure of which is incorporated by reference herein, discloses the joining of a chip to a ceramic substrate wherein support pins control the height of the solder joint between the chip and the ceramic substrate.
Once the integrated circuit component has been joined to the ceramic or organic substrate, the ceramic or organic substrate is usually joined to a second substrate, usually an organic card, to form the second level of packaging. In one preferred method of joining, solder balls on the bottom of the ceramic or organic substrate are joined to mirror image solder balls or pads (which also may be solder-coated) on the second substrate to form a ball grid array, hereafter “BGA”, such as that disclosed in Behun et al. U.S. Pat. No. 5,147,084, the disclosure of which is incorporated by reference herein.
As with the joining of an integrated circuit component to a substrate, increasing the joint height of a BGA is desirable to increase fatigue resistance and reliability.
For example, Foster IBM Technical Disclosure Bulletin, 29, No. 11, pp. 4736-4737 (April 1987), the disclosure of which is incorporated by reference herein, discloses the joining of a ceramic substrate to an organic carrier in which the height of lead/tin eutectic solder joints between the ceramic substrate and organic carrier is controlled by standoffs so as to optimize the fatigue resistance of the joint and maximize reliability.
However, two problems make BGA interconnections more problematical. The first is that the two substrates to be joined are often not flat. One or both substrates may have substantial camber such that it is difficult to make all of the solder connections between the two substrates. The second is that there is considerable interest in going to a lead-free joining solution. While various lead-free solders are known, there is no readily available solder hierarchy given the temperature limitations of an organic carrier so that the low melt/high melt solders methodology often utilized in the aforementioned BGA cannot be used with lead-free solders. The result is that a single-melt solder system must be used which necessitates some method of preventing collapse of the solder joint.
It is, accordingly, one purpose of the present invention to have a BGA interconnection which accommodates camber in the substrates to be joined.
It is another purpose of the present invention to have a BGA interconnection with a single melt solder system and a means to control the height of the solder joint.
It is another purpose of the present invention to have a BGA interconnection with a single melt solder system where the initial height of
Farooq Mukta G.
Jackson Raymond A.
Blecker Ira D.
Cuneo Kamand
Geyer Scott B.
International Business Machines - Corporation
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