Single event upset in SRAM cells in FPGAs with high...

Details Single event upset in SRAM cells in FPGAs with high... Single event upset in SRAM cells in FPGAs with high...

2005-09-30

2008-11-18

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S210000, C257S379000, C257S380000

Reexamination Certificate

active

07452765

ABSTRACT:
SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

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