Single event upset hardened memory cell

Details Single event upset hardened memory cell Single event upset hardened memory cell

1993-08-02

1999-05-18

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

365156, 257379, 257532, H01L29/76

Patent

active

059052902

ABSTRACT:
A bi-stable logic device 110 comprises first and second inverters 112 and 114. A first resistive connection 140 is made between the input 134 of the first inverter 112 and the output B.sub.-- of the second inverter 114 and a second resistive connection 142 is made between the input 138 of the second inverter 114 and the output B of the first inverter 112. The first and said second resistive connections are also capacitively coupling. The device 110 is hardened from single event upset. Other systems and methods are also disclosed.

REFERENCES:
patent: 3767944 (1973-10-01), Stehlin
patent: 4130892 (1978-12-01), Gunckel, II et al.
patent: 4387444 (1983-06-01), Edwards
patent: 4403306 (1983-09-01), Tokushige et al.
patent: 4532609 (1985-07-01), Iizuka
patent: 4725981 (1988-02-01), Rutledge
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 4863878 (1989-09-01), Hite et al.
patent: 4912675 (1990-03-01), Blake et al.
patent: 4914629 (1990-04-01), Blake et al.
patent: 4956814 (1990-09-01), Houston
patent: 5046044 (1991-09-01), Houston et al.
patent: 5204990 (1993-04-01), Houston et al.

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