Single electron transistor using porous silicon and...

Details Single electron transistor using porous silicon and... Single electron transistor using porous silicon and...

2002-03-05

2002-11-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S960000, C257S009000

Reexamination Certificate

active

06479365

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single electron transistor fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof.
2. Description of the Related Art
FIGS. 1A and 1B
are schematic vertical cross-sectional views of conventional single electron transistors. As shown in
FIG. 1A
, a conventional single electron transistor has a structure in which an island
4
is defined by forming two tunnel barriers
5
between a source
2
and a drain
3
on a silicon substrate
1
. As shown in
FIG. 1B
, another conventional single electron transistor has a structure in which a source
12
and a drain
13
are formed on an SOI substrate
11
obtained by forming an SiO
2
insulative layer
11
b
on a silicon substrate
11
a
, and nanometer (nm)-sized granular islands
14
are formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) of a metal or semiconductor within a dielectric
15
.
However, according to a reference document Jpn.J.Appl.Phys 34,12B(1995)6961 by T. Wada et al., in the case of single electron transistors of the type shown in
FIG. 1A
, it is very difficult to uniformly adjust the sizes of the islands
15
to nm-sizes. In particular, according to a reference document Appl.Phys.Lett 68(1996)34 by K. Matsumoto et al., when scanning probe microscopy (SPM) is applied, tunnel barriers deteriorate when exposed to the air, so that the single electron transistor of
FIG. 1A
has no operation reproducibility. According to reference documents Appl.Phys.Lett 66(1995)3383 by W. Chen et al. and Jpn.J.Appl.Phys 36,6B(1997)4038 by A. Dutta et al., in the case of single electron transistors of the type shown in
FIG. 1B
, it is difficult to reproducibly control the distance between the source
12
and the drain
13
which determines the number of islands
14
, and a complicated fabrication process makes it difficult to fabricate the transistors. Therefore, a new structure and a new and simple fabrication method capable of easily adjusting the sizes of islands to nanometer sizes are required in order to realize reproducible single electron transistors which operate at room temperature.
SUMMARY OF THE INVENTION
To solve the above problem, an objective of the present invention is to provide a single electron transistor using porous silicon, which can operate at room temperature and can be applied to next-generation ultra high-density (1-T Byte) memories and logic devices, and a fabrication method thereof.
To achieve the above objective, there is provided a single electron transistor using porous silicon, including: a substrate; a porous silicon layer having pores, each of which has a diameter of 5 nm or less, the porous silicon layer formed as a channel on the substrate; a source and a drain formed of metal on both sides of the porous silicon layer; an insulative layer formed of oxide on the porous silicon layer; and a gate formed on the insulative layer.
It is preferable that the porous silicon layer has a thickness of 10 nm or less.
To achieve the above objective, there is a method of fabricating a single electron transistor using porous silicon, including: (a) forming a porous silicon layer having pores, each of which has a diameter of 5 nm or less by electrochemically etching a 10 nm or thinner silicon layer in a silicon on insulator (SOI) substrate by dipping the SOI substrate into an HF-based solution; (b) securing a source region and a drain region by etching regions of the porous silicon layer at regular intervals, and depositing metal in the source and drain regions, to form a source and a drain each having a thickness of 100 nm or less; and (c) depositing a 10-nm or thinner silicon dioxide layer on the porous silicon layer between the source and drain by chemical vapor deposition, and forming a 100-nm or thinner gate on the silicon dioxide.
In the step (b), preferably, the metal is deposited by physical vapor deposition or chemical vapor deposition. It is also preferable that in steps (b) and (c), the source, drain and gate are formed by a selective etching method or a lift-off process.
To achieve the above objective, there is provided another method of fabricating a single electron transistor using porous silicon, including: (a) exposing portions on which a source and a drain are to be formed, by selectively etching a 10-nm-thick silicon layer included in a silicon on insulator (SOI) substrate, and depositing metal on the exposed portions to have a thickness of 100 nm or less, thereby forming a source and a drain; (b) exposing only the silicon layer by forming resist on the source and drain, and then electrochemically etching the exposed silicon layer by dipping the SOI substrate into an HF-based solution, thereby forming a porous silicon layer having pores, each of which has a diameter of 5 nm or less; and (c) depositing a 10-nm or thinner silicon dioxide-layer on the porous silicon layer by chemical vapor deposition, and forming a 100-nm or thinner gate on the silicon dioxide.
Preferably, in the step (a), the metal is deposited by physical vapor deposition or chemical vapor deposition. It is preferable that in steps (b) and (c), the source, drain and gate are formed by a selective etching method or a lift-off process.
To achieve the above objective, there is provided another single electron transistor using porous silicon, including: a substrate; a porous silicon layer having pores, each of which has a diameter of 5 nm or less, the porous silicon layer formed as a channel on the substrate; a source and a drain formed of silicon doped with impurities on both sides of the porous silicon layer; an insulative layer formed of oxide on the porous silicon layer; and a gate formed on the insulative layer.
Preferably, the porous silicon layer has a thickness of 10 nm or less, and the source and drain are doped with n
+
-type or p
+
-type impurities at a concentration of 10
20
/cm
3
or less.
To achieve the above objective, there is provided a method of fabricating another single electron transistor using porous silicon, comprising: (a) forming resist patterns at regular intervals on a silicon on insulator (SOI) substrate having a 10-nm or thinner silicon layer, and then electrochemically etching an exposed portion of the silicon layer by dipping the SOI substrate into an HF-based solution, thereby forming a porous silicon layer having pores, each of which has a diameter of 5 nm or less; (b) removing the resist patterns, forming resist patterns on only the porous silicon layer to expose the remaining regions on the silicon layer, and depositing impurities on the exposed silicon layer, thereby forming a source and a drain; and (c) depositing a 10-nm or thinner insulative layer on the porous silicon layer by chemical vapor deposition, and forming a 100-nm or thinner gate on the insulative layer.
It is preferable that in the step (b), the impurities are deposited on the silicon layer at a concentration of 10
20
/cm
3
or less by ion-implantation or doping. It is also preferable that in the step (c), the size of each of the silicon pores in the porous silicon layer is adjusted upon formation of SiO
2
and the insulative layer is formed by depositing silicon dioxide to have a thickness of 10 nm or less.
To achieve the above objective, there is provided another method of fabricating another single electron transistor using porous silicon, including: (a) forming a source and a drain by selectively depositing impurities on a 10-nm-thick silicon layer included in a silicon on insulator (SOI) substrate; (b) selectively forming resist on the source and the drain to expose only the silicon layer between the source and the drain, and then electrochemically etching the exposed silicon layer by dipping the SOI substrate into an HF-based solution, thereby forming a porous silicon layer having pores, each of which has a diameter of 5 nm or less; and (c) depositing a 10-nm or thinner insulative layer on the porous silico

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