Single device transfer static latch

Details Single device transfer static latch Single device transfer static latch

1984-08-20

1987-03-31

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, G11C 700

Patent

active

046548262

ABSTRACT:
Each cell of a static latch implemented in MOS transistor circuitry includes an MOS transistor configured to operate a depletion mode and operably coupled to communicate an output node of the cell to an input node of the cell in absence of a control signal, to effect the latching operation. Presence of the control signal allows data to be efficiently written to the cell by enabling a transfer gate to establish a communication path for the data to the input node of the cell, while at the same time disabling the MOS transistor to terminate communication of the output node of the cell to its input node during the write operation.

REFERENCES:
patent: 4445203 (1984-04-01), Iwahashi
patent: 4546455 (1985-10-01), Iwahashi et al.

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