Single damascene integration scheme for preventing copper...

Details Single damascene integration scheme for preventing copper... Single damascene integration scheme for preventing copper...

2006-05-02

2006-05-02

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S751000, C257S760000, C257S762000

Reexamination Certificate

active

07038320

ABSTRACT:
A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

REFERENCES:
patent: 5847459 (1998-12-01), Taniguchi
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6156648 (2000-12-01), Huang
patent: 6331479 (2001-12-01), Li et al.
patent: 6372636 (2002-04-01), Chooi et al.
patent: 6475810 (2002-11-01), Zhou et al.

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