Single cycle refresh of multi-port dynamic random access...

Details Single cycle refresh of multi-port dynamic random access... Single cycle refresh of multi-port dynamic random access...

2006-12-05

2006-12-05

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230050, C365S236000, C365S189050, C365S233100

Reexamination Certificate

active

07145829

ABSTRACT:
A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

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