Single chamber CVD process for thin film transistors

Details Single chamber CVD process for thin film transistors Single chamber CVD process for thin film transistors

1995-06-06

1996-12-31

King, Roy V.

Coating processes

Direct application of electrical, magnetic, wave, or...

Plasma

427578, 427255, 4272551, 4272557, 4272481, 437101, 437909, C23C 1600, B05D 306

Patent

active

055892337

ABSTRACT:
A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.

REFERENCES:
patent: 4609930 (1986-09-01), Yamazaki
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patent: 5221414 (1993-06-01), Langley et al.
patent: 5266504 (1993-11-01), Blouse et al.
patent: 5281546 (1994-01-01), Possin et al.
R. L. Bratter and J. E. Hitchner, "Dielectric Structure as an Out-Diffusion Barrier," IBM Technical Disclosure Bulletin, vol. No. 6, p. 1422, Nov. 1970.

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